TLCS-900/H Instruction Set – Opcode maps

The first byte, and the second byte of each operand class

The first byte of an instruction is looked up in the first-byte map when it is $00–$7F; from $80 it is a prefix and the byte after the operand is looked up in one of the three second-byte maps (memory source, register, destination). A · is an undefined encoding. In the second-byte maps the letters B, W and L show for which operand sizes the second byte is defined; the byte table covers the prefixes $80/$C0 (B), the word table $90/$D0 (W) and the long table $A0/$E0 (L), and likewise for the register prefixes $C7/$C8, $D7/$D8, $E7/$E8.

First byte

x0x1x2x3x4x5x6x7x8x9xAxBxCxDxExF
0xNOPNORMALPUSHPOPMAXHALTEIRETILDPUSHLDWPUSHWINCFDECFRETRETD
1xRCFSCFCCFZCFPUSHPOPEXLDFPUSHPOPJPJPCALLCALLCALR·
2xLDLDLDLDLDLDLDLDPUSHPUSHPUSHPUSHPUSHPUSHPUSHPUSH
3xLDLDLDLDLDLDLDLDPUSHPUSHPUSHPUSHPUSHPUSHPUSHPUSH
4xLDLDLDLDLDLDLDLDPOPPOPPOPPOPPOPPOPPOPPOP
5x········POPPOPPOPPOPPOPPOPPOPPOP
6xJRJRJRJRJRJRJRJRJRJRJRJRJRJRJRJR
7xJRLJRLJRLJRLJRLJRLJRLJRLJRLJRLJRLJRLJRLJRLJRLJRL

Rows 2x to 5x: columns 0–7 load or push or pop the 8 registers of the size of the row ($2x bytes W A B C D E H L; $28+R push a word register; $3x load a word register / $38+R push a long register; $4x load a long register / $48+R pop a word register; $58+R pop a long register). The condition code of rows 6x and 7x is the low nibble. $80–$F5 are the prefixes, $F7 is LDX and $F8–$FF are SWI 0–7.

Second byte after a memory source operand

Prefixes $80–$BF (B $80, W $90, L $A0) and $C0–$C5, $D0–$D5, $E0–$E5. “R” is the 3-bit number in the low bits of the second byte; “m” the memory operand; “#” an immediate after the second byte.

Second byteInstructionSizes
04PUSH mB W
06RLD A,mB
07RRD A,mB
10LDI (XDE+),(XHL+)B W
11LDIRB W
12LDDB W
13LDDRB W
14CPI A,(R+)B W
15CPIRB W
16CPDB W
17CPDRB W
19 + 16-bit addressLD (n16),mB W
20–27LD R,mB W L
30–37EX m,RB W
38 + #ADD m,#B W
39 + #ADC m,#B W
3A + #SUB m,#B W
3B + #SBC m,#B W
3C + #AND m,#B W
3D + #XOR m,#B W
3E + #OR m,#B W
3F + #CP m,#B W
40–47MUL RR,mB W
48–4FMULS RR,mB W
50–57DIV RR,mB W
58–5FDIVS RR,mB W
60–67INC #3,mB W
68–6FDEC #3,mB W
78RLC mB W
79RRC mB W
7ARL mB W
7BRR mB W
7CSLA mB W
7DSRA mB W
7ESLL mB W
7FSRL mB W
80–87ADD R,mB W L
88–8FADD m,RB W L
90–97ADC R,mB W L
98–9FADC m,RB W L
A0–A7SUB R,mB W L
A8–AFSUB m,RB W L
B0–B7SBC R,mB W L
B8–BFSBC m,RB W L
C0–C7AND R,mB W L
C8–CFAND m,RB W L
D0–D7XOR R,mB W L
D8–DFXOR m,RB W L
E0–E7OR R,mB W L
E8–EFOR m,RB W L
F0–F7CP R,mB W L
F8–FFCP m,RB W L

Every second byte not listed is undefined for that size.

Second byte after a register operand

Prefixes $C7/$C8–$CF (B), $D7/$D8–$DF (W), $E7/$E8–$EF (L). “r” is the register of the prefix.

Second byteInstructionSizes
03 + #LD r,#B W L
04PUSH rB W L
05POP rB W L
06CPL rB W
07NEG rB W
08 + #MUL rr,#B W
09 + #MULS rr,#B W
0A + #DIV rr,#B W
0B + #DIVS rr,#B W
0C + d16LINK r,d16L
0DUNLK rL
0EBS1F A,rW
0FBS1B A,rW
10DAA rB
12EXTZ rW L
13EXTS rW L
14PAA rW L
16MIRR rW
19MULA rrW
1C + d8DJNZ r,addrB W
20 + #4ANDCF #4,rB W
21 + #4ORCF #4,rB W
22 + #4XORCF #4,rB W
23 + #4LDCF #4,rB W
24 + #4STCF #4,rB W
28ANDCF A,rB W
29ORCF A,rB W
2AXORCF A,rB W
2BLDCF A,rB W
2CSTCF A,rB W
2E + crLDC cr,rB W L
2F + crLDC r,crB W L
30 + #4RES #4,rB W
31 + #4SET #4,rB W
32 + #4CHG #4,rB W
33 + #4BIT #4,rB W
34 + #4TSET #4,rB W
38 + #16MINC1 #,rW
39 + #16MINC2 #,rW
3A + #16MINC4 #,rW
3C + #16MDEC1 #,rW
3D + #16MDEC2 #,rW
3E + #16MDEC4 #,rW
40–47MUL RR,rB W
48–4FMULS RR,rB W
50–57DIV RR,rB W
58–5FDIVS RR,rB W
60–67INC #3,rB W L
68–6FDEC #3,rB W L
70–7FSCC cc,rB W
80–87ADD R,rB W L
88–8FLD R,rB W L
90–97ADC R,rB W L
98–9FLD r,RB W L
A0–A7SUB R,rB W L
A8–AFLD r,#3B W L
B0–B7SBC R,rB W L
B8–BFEX R,rB W
C0–C7AND R,rB W L
C8 + #ADD r,#B W L
C9 + #ADC r,#B W L
CA + #SUB r,#B W L
CB + #SBC r,#B W L
CC + #AND r,#B W L
CD + #XOR r,#B W L
CE + #OR r,#B W L
CF + #CP r,#B W L
D0–D7XOR R,rB W L
D8–DFCP r,#3B W
E0–E7OR R,rB W L
E8 + #4RLC #4,rB W L
E9 + #4RRC #4,rB W L
EA + #4RL #4,rB W L
EB + #4RR #4,rB W L
EC + #4SLA #4,rB W L
ED + #4SRA #4,rB W L
EE + #4SLL #4,rB W L
EF + #4SRL #4,rB W L
F0–F7CP R,rB W L
F8RLC A,rB W L
F9RRC A,rB W L
FARL A,rB W L
FBRR A,rB W L
FCSLA A,rB W L
FDSRA A,rB W L
FESLL A,rB W L
FFSRL A,rB W L

Every second byte not listed is undefined for that size.

Second byte after a destination operand

Prefixes $B0–$BF and $F0–$F5; the operand has no size of its own.

Second byteInstruction
00 + #8LD m,#8
02 + #16LDW m,#16
04POP m (byte)
06POPW m
14 + address16LD m,(n16) (byte)
16 + address16LDW m,(n16)
20–27LDA RR,m (word register)
28ANDCF A,m
29ORCF A,m
2AXORCF A,m
2BLDCF A,m
2CSTCF A,m
30–37LDA XRR,m (long register)
40–47LD m,R (byte)
50–57LD m,R (word)
60–67LD m,R (long)
80–87ANDCF #3,m
88–8FORCF #3,m
90–97XORCF #3,m
98–9FLDCF #3,m
A0–A7STCF #3,m
A8–AFTSET #3,m
B0–B7RES #3,m
B8–BFSET #3,m
C0–C7CHG #3,m
C8–CFBIT #3,m
D0–DFJP cc,m
E0–EFCALL cc,m
F0–FFRET cc (only with the prefix B0; the operand is not used)

Every second byte not listed is undefined.

Not described

  • The maps are the encodings the decoder and the RACE core agree on (status page); no printed code map of the manual was read to compare them.
  • RACE also defines the register-table slot 1A (second byte after $C7, $C8–$CF) as a hook for its own BIOS emulation; it is not part of the instruction set and is shown as undefined.