The prefix scheme
An instruction whose first byte is $80 or more is prefix, [operand bytes], second byte, [immediate]. The prefix chooses the operand and its size; the second byte chooses the operation
from the table of that class (see the opcode maps). The operand is usually the source (ADD A,(XIX+5)) or the register of a register-to-register operation, and
the destination classes ($B0–$BF, $F0–$F5) hold the memory forms where the operand is written or only its address matters (LD (mem),#8, LDA, JP cc,(mem)).
| Prefix | Operand | Class (second-byte table) |
|---|---|---|
$80–$87 | (XWA) (XBC) (XDE) (XHL) (XIX) (XIY) (XIZ) (XSP), register number in the low 3 bits | MB: byte memory |
$88–$8F | (XWA+d8) … (XSP+d8): one signed byte follows | MB |
$90–$97, $98–$9F | the same, word operand | MW: word memory |
$A0–$A7, $A8–$AF | the same, long operand | ML: long memory |
$B0–$B7, $B8–$BF | the same, no size (destination or address) | D: destination memory |
$C0 $D0 $E0 $F0 | (n8): an 8-bit absolute address (0 to 255) | MB, MW, ML, D |
$C1 $D1 $E1 $F1 | (n16): a 16-bit absolute address | MB, MW, ML, D |
$C2 $D2 $E2 $F2 | (n24): a 24-bit absolute address | MB, MW, ML, D |
$C3 $D3 $E3 $F3 | a complex operand: a mode byte follows (below) | MB, MW, ML, D |
$C4 $D4 $E4 $F4 | (-XIX): pre-decrement, then a register code byte | MB, MW, ML, D |
$C5 $D5 $E5 $F5 | (XIX+): post-increment, then a register code byte | MB, MW, ML, D |
$C6 $D6 $E6 $F6 | not defined | – |
$C7 $D7 $E7 | a register, named by a code byte (register codes), byte, word, long | RB, RW, RL |
$C8–$CF $D8–$DF $E8–$EF | a register of the current bank, 3-bit number in the low bits (byte W A B C D E H L, word WA … SP, long XWA … XSP) | RB, RW, RL |
$F7 | LDX, a fixed six-byte instruction | – |
$F8–$FF | SWI 0 to SWI 7 | – |
Bytes $F7 and $F8 to $FF have no class: the destination prefixes stop at $F5, and the second-byte forms of RET cc exist only with $B0.
Memory operand forms
| Form | Written | Bytes after the prefix | Notes |
|---|---|---|---|
| register indirect | (XIX) | 0 (prefix $80–$87…) or 1 register code ($C3 mode 0) | The mode byte of $C3 carries the register code with the two low bits 00, so any bank register can be used. |
| indirect + 8-bit displacement | (XIX+5) | 1: signed displacement | Only with the prefixes $88–$8F, $98–$9F, $A8–$AF, $B8–$BF, so only for the eight registers of the current bank and the global ones. |
| indirect + 16-bit displacement | (XIX+$1234) | $C3, mode byte = code with low bits 01, 2 displacement bytes | |
| indirect + 8-bit register | (XIX+C) | $C3, $03, 32-bit register code, 8-bit register code | The index register is a signed byte register. |
| indirect + 16-bit register | (XIX+BC) | $C3, $07, 32-bit register code, 16-bit register code | The index register is a signed word register. |
| absolute 8-bit | ($20) | 1 | An address in $000000–$0000FF: the Neo Geo Pocket’s CPU-internal I/O registers are here. |
| absolute 16-bit | ($6F80) | 2 | Zero-extended: $000000–$00FFFF. |
| absolute 24-bit | ($200040) | 3 | Any address of the 16 MiB space. |
| PC relative | (PC+$0010) | $C3, $13, 2 displacement bytes | The displacement is added to the address after the displacement (the prefix, the mode byte and the two bytes: address + 4); the viewer shows the address. LDA R,(PC+d16) is written LDAR R,address. |
| pre-decrement | (-XIX) | prefix $C4…: 1 register code byte | The two low bits of the code give the step: 0 = 1 byte, 1 = 2, 2 = 4 (3 is not defined and is shown as reserved). The register is decremented, then used. |
| post-increment | (XIX+) | prefix $C5…: 1 register code byte | The same step code; the register is used, then incremented. The viewer does not write the step (it is in the operand bytes); in the Snake ROM it is 4 for a long operand (E5 F2 20). |
A register code that is not a 32-bit register ($40–$CF, or one whose two low bits are not zero where zero is needed) decodes with the same length and the status reserved.
The second byte and what follows it
After the operand bytes comes the second byte. Many second bytes carry a 3-bit register or number in their low bits (ADD R,(mem) is $80 + R; INC #3,(mem) is $60 + n, n = 0 meaning 8), and some carry a
condition code in their low nibble. The bytes after the second byte are, in this order, a 16-bit address (LD (n16),(mem)), an immediate (ADD (mem),#, LD r,#), a relative displacement (DJNZ) or a bit number, shift count
or control register code (RES #4,r, SLA #4,r, LDC cr,r). Immediate size follows the operation size: 1, 2 or 4 bytes.
The longest instruction is seven bytes: a prefix, a three-byte complex operand, the second byte and a 16-bit immediate or address.
Instructions with a fixed prefix
LDI,LDIR,LDD,LDDR(and the word formsLDIW…): prefix$83((XDE+),(XHL+)) or$85((XIX+),(XIY+)), word forms$93and$95. With any other prefix the viewer decodes the same length with the status reserved.CPI,CPIR,CPD,CPDR: prefix$80–$87(byte, againstA) or$90–$97(word, againstWA): the prefix names the pointer register.RET cc: prefix$B0and second byte$F0+ cc.LDX:$F7 00 n 00 d 00stores the bytedat the 8-bit addressn. The bytes of the instruction that are 0 in the manual are checked by the viewer (anything else: reserved).
Not described
- Which register-code values the manual allows in each complex form beyond what the CPU of the RACE core accepts.
- The behaviour of an undefined prefix such as
$C6(shown as illegal, one byte).