Signetics 2650 Instruction Set – Registers and the status word

R0 to R6, the instruction address register, the return stack, and the program status word PSU and PSL

Introduction

The programmer sees seven 8-bit registers, a 15-bit instruction address register, an eight-level return stack and the program status word (PSW), which is two bytes: the upper byte PSU and the lower byte PSL. Most arithmetic works on a register and one other operand; R0 is the register that the register-to-register instructions and the indexed absolute instructions use as the other operand.

The registers

RegisterSizeNotes
R08 bitsAlways the same register. The accumulator of the Z instructions (ADDZ,R2 is R0 = R0 + R2) and the data register of every indexed absolute instruction.
R1, R2, R38 bitsThe registers an opcode names with its low two bits (value 1 to 3). Bit RS of the PSL selects which of two banks the names mean: with RS clear they are the first bank, with RS set the second. The second bank is also written R4, R5, R6 (the registers option of the viewer shows the second bank that way).
R38 bitsAlso the implied index register of BXA and BSXA.
IAR13 bits + 2 page bitsThe instruction address register: the address of the next instruction, 15 bits. The low 13 bits count up inside the 8 KB page: an instruction at the end of a page continues at the start of the same page (as the core read here does it).
Return stack8 x 15 bitsSubroutine calls (BSTR, BSTA, BSNR, BSNA, BSFR, BSFA, ZBSR, BSXA) push the address of the next instruction; returns (RETC, RETE) pop it. The stack pointer is the three low bits of PSU. A call is pre-incrementing in the core read: SP = SP + 1, then the return address is stored at the new SP; a return reads the entry at SP, then SP = SP - 1. Nothing detects overflow: the ninth call overwrites the oldest entry.

Program status upper (PSU)

BitNameMeaning
7 ($80)SSense input: the state of the sense pin (on the Arcadia, a video blanking line). Read-only: PPSU, LPSU and CPSU cannot change it. Read with SPSU or TPSU.
6 ($40)FFlag output: a pin the program sets and clears with PPSU and CPSU.
5 ($20)IIInterrupt inhibit: while set, interrupts are not taken. Set when an interrupt is taken; RETE clears it.
4, 3–Unused. The core read here never sets them (PPSU cannot set them, LPSU clears them); one modern compatible chip documents bit 4 as readable and writable.
2 to 0 ($07)SPThe return stack pointer, 0 to 7.

Program status lower (PSL)

BitNameMeaning
7, 6 ($C0)CCThe condition code, described below. Set by most instructions that produce a value; the conditional branches and returns test it.
5 ($20)IDCInter-digit carry: the carry from bit 3 into bit 4 of an addition or subtraction (and of a rotate with carry), used by DAR.
4 ($10)RSRegister bank select. Changing it (PPSL, CPSL, LPSL) makes R1 to R3 mean the other three registers.
3 ($08)WCWith carry: when set, add, subtract and the rotates use the carry flag C as the carry in (and rotate through it); when clear they ignore it and rotate eight bits.
2 ($04)OVFTwo’s-complement overflow of an addition or subtraction.
1 ($02)COMCompare mode: clear, COM instructions compare as signed numbers; set, as unsigned numbers.
0 ($01)CCarry (for subtraction, set when there is no borrow). Written by add, subtract and, with WC set, the rotates.

The condition code

CCCondition namesSet when
0EQ (zero, equal)the result is zero; a compare found the operands equal; a test under mask found every tested bit set
1GT (positive, greater)the result is positive (bit 7 clear, not zero); the register is greater than the operand
2LT (negative, less)the result is negative (bit 7 set); the register is less; a test under mask found a tested bit clear
3UNno instruction produces 3 as a result (LPSL can load it). In a branch or return, the condition field 3 means unconditional; in the false-condition branches (BCFR and the others) the field value 3 is not a condition at all: those four opcodes are ZBRR, BXA, ZBSR and BSXA.

Instructions that set the condition code from their result: all LOD, EOR, AND, IOR, ADD, SUB, STRZ, the rotates, REDC, REDD, REDE, SPSU and SPSL. COM sets it from the comparison, and TMI, TPSU and TPSL set it to 0 or 2. The stores STRR and STRA, the branches, BIR and BDR and DAR leave it alone (in the core read here; the Arcadia emulator on emulators.org also sets it on every store, which the FBNeo core does not).

Reset and interrupts

After a reset the processor starts at address 0 (the Arcadia’s cartridge begins there). The sources read differ on the other state: the core read here starts with PSL = COM + WC and PSU = 0; the Avalon page gives a PSU of $20 (interrupts inhibited) and a PSL of 0; the Wikibook says reset clears II and advises a program to set up PSU, PSL and the stack pointer itself. This page does not choose.

An interrupt (the Arcadia’s video chip raises one) is taken after the current instruction when II is clear: II is set, the next address is pushed on the return stack and the processor branches as a ZBSR would, with the displacement byte put on the data bus by the interrupting device; the Wikibook says the Arcadia’s video chip gives vector 3, so the handler starts at $0003. The handler leaves with RETE, which also clears II.

Not described

Known, not yet covered

  • Reference: the exact timing of the interrupt sequence and the pins (SENSE, FLAG, the I/O strobes), which belong to the machine pages.

Unknown

  • Reference: the reset values of PSU and PSL (the sources disagree), what a real chip does when the return stack overflows, and whether bits 4 and 3 of PSU can be written on the 2650, 2650A and 2650B.

Links

Reference