Signetics 2650 Instruction Set – Opcode map

All 256 opcodes: 246 instructions and ten undefined

Introduction

The row is the high nibble of the opcode and the column the low nibble. In almost every group of four columns the low two bits are a register (0 to 3) or, in the branches and returns, a condition (EQ, GT, LT, UN); bits 3 and 2 select the addressing mode in the data instructions (0 register Z, 1 immediate I, 2 relative R, 3 absolute A). The undefined opcodes are shaded. Four opcodes reuse the condition-3 slot of a group of branches: 9B is ZBRR, 9F is BXA, BB is ZBSR and BF is BSXA. Opcode 40 (ANDZ,R0) is HALT and C0 (STRZ,R0) is NOP.

The map

x0x1x2x3x4x5x6x7x8x9xAxBxCxDxExF
0xLODZLODZLODZLODZLODILODILODILODILODRLODRLODRLODRLODALODALODALODA
1x--SPSUSPSLRETCRETCRETCRETCBCTRBCTRBCTRBCTRBCTABCTABCTABCTA
2xEORZEORZEORZEORZEORIEORIEORIEORIEORREORREORREORREORAEORAEORAEORA
3xREDCREDCREDCREDCRETERETERETERETEBSTRBSTRBSTRBSTRBSTABSTABSTABSTA
4xHALTANDZANDZANDZANDIANDIANDIANDIANDRANDRANDRANDRANDAANDAANDAANDA
5xRRRRRRRRRRRRREDEREDEREDEREDEBRNRBRNRBRNRBRNRBRNABRNABRNABRNA
6xIORZIORZIORZIORZIORIIORIIORIIORIIORRIORRIORRIORRIORAIORAIORAIORA
7xREDDREDDREDDREDDCPSUCPSLPPSUPPSLBSNRBSNRBSNRBSNRBSNABSNABSNABSNA
8xADDZADDZADDZADDZADDIADDIADDIADDIADDRADDRADDRADDRADDAADDAADDAADDA
9x--LPSULPSLDARDARDARDARBCFRBCFRBCFRZBRRBCFABCFABCFABXA
AxSUBZSUBZSUBZSUBZSUBISUBISUBISUBISUBRSUBRSUBRSUBRSUBASUBASUBASUBA
BxWRTCWRTCWRTCWRTCTPSUTPSL--BSFRBSFRBSFRZBSRBSFABSFABSFABSXA
CxNOPSTRZSTRZSTRZ----STRRSTRRSTRRSTRRSTRASTRASTRASTRA
DxRRLRRLRRLRRLWRTEWRTEWRTEWRTEBIRRBIRRBIRRBIRRBIRABIRABIRABIRA
ExCOMZCOMZCOMZCOMZCOMICOMICOMICOMICOMRCOMRCOMRCOMRCOMACOMACOMACOMA
FxWRTDWRTDWRTDWRTDTMITMITMITMIBDRRBDRRBDRRBDRRBDRABDRABDRABDRA

The undefined opcodes

Opcodes 10, 11, 90, 91, B6, B7 and C4 to C7 have no instruction in the 2650. The explorer shows each as a one-byte DB with the status Illegal. What a real chip does is not documented in the sources read: the MAME-derived core executes them as a no-operation of 7 clock cycles, and the AS2650-2, a modern compatible chip, uses them for new instructions (push, pop, multiply, exchange, an extension prefix and clear), so they are not safe to use in a program meant to run on other hardware. C4 to C7 would be an immediate store (STRI), which the 2650 does not have; the register-to-register forms ANDZ,R0 and STRZ,R0 are the instructions HALT and NOP.

Not described

Known, not yet covered

  • Reference: the extended instruction set of the AS2650-2 (not a 2650 instruction set; later, if a machine uses it).

Unknown

  • Reference: the behaviour of the ten undefined opcodes on real 2650, 2650A and 2650B chips.

Links

Reference