What the HD6309 adds
Hitachi’s HD6309 (also sold as the HD63B09) runs every MC6809 program. In its data sheets it is a 6809; the extra instructions below were left undocumented by Hitachi and were worked out by users, so all of this page rests on third-party descriptions (the opcode list of sbprojects.net read with WebFetch on 2026-11-13, plus the illegal-opcode facts of the 6809Decoder wiki). The additions need the HD6309 choice of processor in the viewer: with MC6809 chosen these opcodes are shown as illegal.
A second register file: W (16 bits, E high and F low), Q (32 bits: D high, W low), V (16 bits), a zero register that reads as 0, and the mode register MD.
E and F have their own load, store, add, subtract and compare; W acts as a second accumulator and as an index register.
The chip has an emulation mode (after reset, 6809 timing and 6809 interrupt stacking) and a native mode (MD bit 0: faster, and interrupts also push E and F).
Cycle counts are not given here.
Register to register: ADDR, ADCR, SUBR, SBCR, ANDR, ORR, EORR, CMPR
Opcodes $1030 to $1037 in that order, followed by a register-pair postbyte like TFR’s (source high nibble, destination low), with the 6309 codes of the
TFR table (W, V, E, F and the zero register included). The result goes into the destination (not for CMPR). 3 bytes.
Accumulator instructions on D, W, E and F
| Register | Instructions | Opcodes |
|---|---|---|
D | NEGD COMD LSRD RORD ASRD ASLD ROLD DECD INCD TSTD CLRD | 1040 1043 1044 1046 1047 1048 1049 104A 104C 104D 104F |
W | COMW LSRW RORW ROLW DECW INCW TSTW CLRW | 1053 1054 1056 1059 105A 105C 105D 105F |
E | COME DECE INCE TSTE CLRE | 1143 114A 114C 114D 114F |
F | COMF DECF INCF TSTF CLRF | 1153 115A 115C 115D 115F |
All are inherent and 2 bytes, and set flags as the 8-bit and 16-bit instruction of the same name does on A, B or D. There is no NEGW or NEGE.
D, W, E and F against memory
| Group | Instructions | Opcodes (immediate, direct, indexed, extended) |
|---|---|---|
| W, 16 bit | SUBW CMPW LDW STW ADDW | 1080 1090 10A0 10B0 · 1081 … · 1086 … · STW 1097 10A7 10B7 · 108B … |
| D, 16 bit | SBCD ANDD BITD EORD ADCD ORD | 1082 1084 1085 1088 1089 108A with +10, +20, +30 for direct, indexed, extended |
| E, 8 bit | SUBE CMPE LDE STE ADDE | 1180 1181 1186 118B and STE 1197 11A7 11B7 |
| F, 8 bit | SUBF CMPF LDF STF ADDF | 11C0 11C1 11C6 11CB and STF 11D7 11E7 11F7 |
The rows follow the pattern of the MC6809’s accumulator rows: the immediate form is $1080 + n, direct $1090 + n, indexed $10A0 + n, extended $10B0 + n for the page-2 group, and the same with
$1180 or $11C0 for E and F. The full list of 436 opcodes is in the maps.
MULD, DIVD and DIVQ
| Instruction | Opcodes (immediate, direct, indexed, extended) | Operand |
|---|---|---|
DIVD | 118D 119D 11AD 11BD | an 8-bit divisor (immediate form 3 bytes) |
DIVQ | 118E 119E 11AE 11BE | a 16-bit divisor (immediate form 4 bytes) |
MULD | 118F 119F 11AF 11BF | a 16-bit multiplier (immediate form 4 bytes) |
The viewer’s one-line summaries: DIVD divides D by the byte (quotient in B, remainder in A); DIVQ divides Q by the word (quotient in W, remainder in D);
MULD multiplies D by the word into Q. The source read for the opcode list does not give the result registers; these summaries are unchecked, and a division by zero takes the trap at $FFF0.
LDQ and STQ
Load and store the 32-bit register Q (D high, W low): LDQ #n32 is the single opcode $CD followed by four bytes (5 bytes in all);
LDQ direct, indexed, extended is $10DC $10EC $10FC and STQ is $10DD $10ED $10FD.
Bit instructions: BAND, BIAND, BOR, BIOR, BEOR, BIEOR, LDBT, STBT
Opcodes $1130 to $1137 in that order, then a postbyte, then a direct address (4 bytes). The postbyte: bits 7 and 6 name the register (00 CC, 01 A, 10 B; 11 is the zero register),
bits 5 to 3 a bit number and bits 2 to 0 a second bit number. The viewer writes them as reg,bits 5–3,bits 2–0,address; which of the two is the register’s bit and which the memory’s is called “source”
and “destination” by the source we read, which does not say more, so it is not stated here.
TFM: block transfer
$1138 TFM r0+,r1+, $1139 TFM r0-,r1-, $113A TFM r0+,r1, $113B TFM r0,r1+, followed by a postbyte with the two registers (source high nibble, destination low), each one of
D X Y U S (codes 0 to 4; another code takes the illegal-instruction trap). It copies W bytes (or does nothing if W is 0). 3 bytes.
BITMD and LDMD: the mode register
$113C BITMD #n tests bits of the mode register and $113D LDMD #n loads it. 3 bytes. The bits of MD (native mode, FIRQ stacking, divide-by-zero and illegal-opcode flags) are not described here.
OIM, AIM, EIM and TIM
Read-modify-write on memory with an immediate byte: OIM #n,addr $01 $61 $71, AIM $02 $62 $72, EIM $05 $65 $75, TIM $0B $6B $7B (direct, indexed, extended). The immediate byte comes
first, then the address or the indexed postbyte. TIM only tests. The HD6303 has these four as well, at other opcodes: see 6800, 6801 and 6303.
SEXW and the W stack instructions; the W index forms
$14 SEXW sign-extends W into D (note: the 6809 leaves $14 undefined). $1038 PSHSW, $1039 PULSW, $103A PSHUW, $103B PULUW push and pull W on the S or U stack (2 bytes).
The indexed postbytes for E,R, F,R, W,R, ,W, n16,W, ,W++, ,--W and their indirect forms are in the
indexed table.
Illegal instructions
The 330 opcodes that neither the MC6809 nor these additions define, the seven undefined indexed postbytes and a TFM with a register other than D X Y U S all take the illegal-instruction trap through the vector at
$FFF0. A write to the zero register through TFR, EXG or a bit instruction is ignored without a trap.
Not described
- Cycle counts (emulation and native mode), the bits of
MD, interrupt stacking in native mode, the exact flags of the register, bit, multiply and divide instructions, and the result registers ofDIVD,DIVQ,MULDbeyond the summary above. - No executing HD6309 core was available: the decoder is checked against two opcode tables (the 436 opcodes of the sbprojects list and the wiki’s counts), not run.