6809 Instruction Set: Instructions

Reading the tables

Opcodes are in hex; a four-digit opcode starts with a prefix ($10 page 2, $11 page 3). Operand forms: #n immediate, dir direct, idx indexed, ext extended; where a row gives four opcodes they are in that order (immediate or inherent, direct, indexed, extended). Cycles are the data sheet’s: for the indexed form the count is for ,R without offset plus the postbyte’s extra cycles (shown as +). Flags lists the condition codes the instruction changes; 0 and 1 mean “always cleared” and “always set”, and a flag that the data sheet calls undefined is left out. Where an instruction exists for several registers its row covers them all. The HD6309’s extra instructions are on their own page.

Loads, stores, transfers and the stack

Mnemonic	Opcodes	Bytes	Cycles	Flags	What it does
`LDA` `LDB` `LDD` `LDX` `LDU` `LDY` `LDS`	`86 96 A6 B6` · `C6 D6 E6 F6` `CC DC EC FC` · `8E 9E AE BE` · `CE DE EE FE` `108E 109E 10AE 10BE` · `10CE 10DE 10EE 10FE`	2/2/2+/3 (8 bit); 3/2/2+/3 (16 bit); one more for LDY and LDS	8 bit: 2 4 4+ 5; 16 bit: 3 5 5+ 6; LDY, LDS: 4 6 6+ 7	N Z, V=0	Load a register from an operand. Immediate operands are 8 or 16 bits.
`STA` `STB` `STD` `STX` `STU` `STY` `STS`	`97 A7 B7` · `D7 E7 F7` `DD ED FD` · `9F AF BF` · `DF EF FF` `109F 10AF 10BF` · `10DF 10EF 10FF`	2/2+/3 (8 bit and 16 bit); one more for STY and STS	8 bit: 4 4+ 5; 16 bit: 5 5+ 6; STY, STS: 6 6+ 7	N Z, V=0	Store a register. There is no immediate form: `$87` and `$8F` are undefined.
`LEAX` `LEAY` `LEAS` `LEAU`	`30` `31` `32` `33`	2+	4+	Z (LEAX and LEAY only)	Load the effective address of an indexed operand into the register: adds the offset without reading memory. `LEAX 1,X` is the usual increment.
`TFR`	`1F`	2	6	CC if CC is the destination	Copy one register to another: source in the high nibble of the postbyte, destination in the low. See the codes.
`EXG`	`1E`	2	8	CC if CC is a register	Exchange two registers.
`PSHS`	`34`	2	5 + bytes	none	Push the registers named in the mask on the S stack (`PC` first). See the masks.
`PULS`	`35`	2	5 + bytes	all, if CC is pulled	Pull registers from the S stack. With bit 7 set it pulls PC and so returns.
`PSHU`	`36`	2	5 + bytes	none	Push on the U stack (bit 6 is S).
`PULU`	`37`	2	5 + bytes	all, if CC is pulled	Pull from the U stack.

Arithmetic and comparison

Mnemonic	Opcodes	Bytes	Cycles	Flags	What it does
`ADDA` `ADDB` `ADDD`	`8B 9B AB BB` · `CB DB EB FB` `C3 D3 E3 F3`	2/2/2+/3 · 3/2/2+/3 (ADDD)	8 bit: 2 4 4+ 5; ADDD: 4 6 6+ 7	H N Z V C (ADDD: N Z V C)	Add to A, B or D.
`ADCA` `ADCB`	`89 99 A9 B9` · `C9 D9 E9 F9`	2/2/2+/3	2 4 4+ 5	H N Z V C	Add with the carry flag.
`SUBA` `SUBB` `SUBD`	`80 90 A0 B0` · `C0 D0 E0 F0` `83 93 A3 B3`	as ADD	8 bit: 2 4 4+ 5; SUBD: 4 6 6+ 7	N Z V C	Subtract from A, B or D.
`SBCA` `SBCB`	`82 92 A2 B2` · `C2 D2 E2 F2`	2/2/2+/3	2 4 4+ 5	N Z V C	Subtract with borrow.
`CMPA` `CMPB` `CMPD` `CMPX` `CMPY` `CMPU` `CMPS`	`81 91 A1 B1` · `C1 D1 E1 F1` `1083 1093 10A3 10B3` · `8C 9C AC BC` `108C 109C 10AC 10BC` · `1183 1193 11A3 11B3` · `118C 119C 11AC 11BC`	8 bit: 2/2/2+/3; 16 bit: 3/2/2+/3; page 2 and 3: one more	8 bit: 2 4 4+ 5; CMPX: 4 6 6+ 7; CMPD, CMPY, CMPU, CMPS: 5 7 7+ 8	N Z V C	Compare: subtract and keep only the flags.
`NEG` `NEGA` `NEGB`	`00 60 70` · `40` · `50`	2 2+ 3 · 1	6 6+ 7 · 2	N Z V C	Two’s complement of memory or a register.
`INC` `INCA` `INCB`	`0C 6C 7C` · `4C` · `5C`	2 2+ 3 · 1	6 6+ 7 · 2	N Z V	Add one (C is not changed).
`DEC` `DECA` `DECB`	`0A 6A 7A` · `4A` · `5A`	2 2+ 3 · 1	6 6+ 7 · 2	N Z V	Subtract one (C is not changed).
`MUL`	`3D`	1	11	Z C	Unsigned `A × B` into `D`. C is bit 7 of the result’s low byte (rounding).
`DAA`	`19`	1	2	N Z C	Decimal adjust A after an addition of two BCD bytes.
`SEX`	`1D`	1	2	N Z	Sign-extend B into A (so `D` holds the 16-bit value).
`ABX`	`3A`	1	3	none	Add B, unsigned, to X.

Logic, shifts and bit tests

Mnemonic	Opcodes	Bytes	Cycles	Flags	What it does
`ANDA` `ANDB`	`84 94 A4 B4` · `C4 D4 E4 F4`	2/2/2+/3	2 4 4+ 5	N Z, V=0	AND into A or B.
`ORA` `ORB`	`8A 9A AA BA` · `CA DA EA FA`	2/2/2+/3	2 4 4+ 5	N Z, V=0	OR into A or B.
`EORA` `EORB`	`88 98 A8 B8` · `C8 D8 E8 F8`	2/2/2+/3	2 4 4+ 5	N Z, V=0	Exclusive OR into A or B.
`BITA` `BITB`	`85 95 A5 B5` · `C5 D5 E5 F5`	2/2/2+/3	2 4 4+ 5	N Z, V=0	AND without storing the result.
`COM` `COMA` `COMB`	`03 63 73` · `43` · `53`	2 2+ 3 · 1	6 6+ 7 · 2	N Z, V=0, C=1	One’s complement.
`LSR` `LSRA` `LSRB`	`04 64 74` · `44` · `54`	2 2+ 3 · 1	6 6+ 7 · 2	N=0, Z C	Logical shift right: bit 0 goes to C.
`ROR` `RORA` `RORB`	`06 66 76` · `46` · `56`	2 2+ 3 · 1	6 6+ 7 · 2	N Z C	Rotate right through C.
`ASR` `ASRA` `ASRB`	`07 67 77` · `47` · `57`	2 2+ 3 · 1	6 6+ 7 · 2	N Z C	Arithmetic shift right: bit 7 is kept.
`ASL` `ASLA` `ASLB` (= `LSL`)	`08 68 78` · `48` · `58`	2 2+ 3 · 1	6 6+ 7 · 2	N Z V C	Shift left: bit 7 goes to C.
`ROL` `ROLA` `ROLB`	`09 69 79` · `49` · `59`	2 2+ 3 · 1	6 6+ 7 · 2	N Z V C	Rotate left through C.
`TST` `TSTA` `TSTB`	`0D 6D 7D` · `4D` · `5D`	2 2+ 3 · 1	6 6+ 7 · 2	N Z, V=0	Compare with zero.
`CLR` `CLRA` `CLRB`	`0F 6F 7F` · `4F` · `5F`	2 2+ 3 · 1	6 6+ 7 · 2	N=0 Z=1 V=0 C=0	Clear memory or a register. The MC6809 reads the memory location before it clears it.

Branches, jumps and interrupts

Each conditional short branch Bcc (opcodes 21 to 2F) has a long form LBcc with the prefix $10 and the same second byte, and a 16-bit displacement. A short branch takes 3 cycles whether or not it is taken; a long one takes 5, or 6 when taken (LBRA 5, LBSR 9).

Mnemonic	Opcode	Condition	Flags read
`BRA` `LBRA`	`20` · `16`	always	–
`BRN` `LBRN`	`21` · `1021`	never	–
`BHI` `LBHI`	`22` · `1022`	higher (unsigned): C=0 and Z=0	C Z
`BLS` `LBLS`	`23` · `1023`	lower or same (unsigned)	C Z
`BCC` `LBCC` (`BHS`)	`24` · `1024`	carry clear: higher or same	C
`BCS` `LBCS` (`BLO`)	`25` · `1025`	carry set: lower	C
`BNE` `LBNE`	`26` · `1026`	not equal: Z=0	Z
`BEQ` `LBEQ`	`27` · `1027`	equal: Z=1	Z
`BVC` `LBVC`	`28` · `1028`	overflow clear	V
`BVS` `LBVS`	`29` · `1029`	overflow set	V
`BPL` `LBPL`	`2A` · `102A`	plus: N=0	N
`BMI` `LBMI`	`2B` · `102B`	minus: N=1	N
`BGE` `LBGE`	`2C` · `102C`	greater or equal (signed)	N V
`BLT` `LBLT`	`2D` · `102D`	less than (signed)	N V
`BGT` `LBGT`	`2E` · `102E`	greater than (signed)	N V Z
`BLE` `LBLE`	`2F` · `102F`	less or equal (signed)	N V Z

Mnemonic	Opcodes	Bytes	Cycles	Flags	What it does
`LBRA`	`16`	3	5	none	Branch always with a 16-bit displacement.
`LBSR`	`17`	3	9	none	Long branch to subroutine: pushes the return address on S.
`BSR`	`8D`	2	7	none	Branch to subroutine.
`JSR`	`9D AD BD`	2 2+ 3	7 7+ 8	none	Jump to subroutine at the effective address.
`JMP`	`0E 6E 7E`	2 2+ 3	3 3+ 4	none	Jump to the effective address (no memory is read, except the pointer of an indirect form).
`RTS`	`39`	1	5	none	Pull PC from S.
`RTI`	`3B`	1	6, or 15 with E set	all	Return from interrupt: pulls CC, then, if E is set, A B DP X Y U, then PC.
`SWI`	`3F`	1	19	E F I	Software interrupt: pushes the whole state, masks F and I, jumps through `$FFFA`.
`SWI2`	`103F`	2	20	E	Software interrupt 2, through `$FFF4`; it does not mask interrupts.
`SWI3`	`113F`	2	20	E	Software interrupt 3, through `$FFF2`.
`CWAI`	`3C`	2	20+	all (AND mask)	AND CC with the byte, set E, push the whole state and wait for an interrupt.
`SYNC`	`13`	1	4+	none	Wait for an interrupt line to go active; it continues without taking a masked interrupt.

Condition codes and no-operation

Mnemonic	Opcodes	Bytes	Cycles	Flags	What it does
`NOP`	`12`	1	2	none	No operation.
`ORCC`	`1A`	2	3	any	OR the byte into CC: sets flags (`orcc #$50` masks both interrupts).
`ANDCC`	`1C`	2	3	any	AND the byte into CC: clears flags.

The undefined opcodes of page 1 are 01 02 05 0B 14 15 18 1B 38 3E 41 42 45 4B 4E 51 52 55 5B 5E 61 62 65 6B 71 72 75 7B 87 8F C7 CD CF and the ones on pages 2 and 3 listed on the opcode maps. (On the HD6309 01 02 05 0B 14 61 62 65 6B 71 72 75 7B CD are defined.)

Not described

Interrupt entry and exit sequences beyond what each instruction’s row says; bus timing.
The behaviour of undefined opcodes on a real MC6809.

6809 Instruction Set – Instructions