PDP-11 Registers, PSW and memory

Registers

Register	Name	Use
R0 to R5	`r0` to `r5`	General purpose. Any instruction can use any of them as an accumulator, an index or a pointer. (Some instructions use pairs: MUL, DIV and ASHC take R and R+1.)
R6	`sp`	The stack pointer. The stack grows towards lower addresses: a push decrements SP by 2 and stores, a pop loads and increments by 2. Traps, interrupts and JSR use it. On the models with memory management each of kernel, supervisor and user mode has its own R6.
R7	`pc`	The program counter. It points at the next word to fetch: while an instruction executes, PC is already past the instruction word and past each operand word fetched so far. That is why a branch is counted from the address after the branch and why the relative modes work (addressing modes).

The models with memory management (the 11/45, 11/70 and later) have two sets of R0 to R5, selected by one bit of the status word, so an interrupt routine can have its own. The disassembler does not show which set is in use.

R6 and R7 are always used as whole words and an odd value in either is an error: a byte autoincrement or autodecrement through SP or PC changes the register by 2, not 1, so the stack stays even.

The processor status word

The status word (PSW) holds the condition codes, the trace bit, the interrupt priority and, on the models with memory management, the processor modes and the register-set bit. On the models that map it, it is also a memory word at address 177776; the LSI-11 does not map it, and the instructions MFPS and MTPS are the way to reach its low byte there.

Bits	Name	Meaning
15–14	current mode	00 kernel, 01 supervisor, 11 user (10 is not used)
13–12	previous mode	the mode before the last trap: used by MFPI, MTPI and the data-space forms
11	register set	which of the two sets of R0 to R5 is in use
7–5	priority	the processor priority, 0 to 7; a device interrupts only if its priority is higher. Set by SPL or by loading the PSW
4	T	the trace bit: after each instruction the processor traps through vector 14
3	N	negative: the result’s top bit
2	Z	zero: the result was zero
1	V	overflow: the signed result did not fit
0	C	carry: a carry out of (or borrow into) the top bit; for the shifts, the bit shifted out

The condition codes are set by most instructions (each instruction’s page entry gives its flags). The branch instructions test them: BNE and BEQ test Z, the signed branches BGE, BLT, BGT and BLE test N, V and Z together, the unsigned BHI, BLOS, BCC (BHIS) and BCS (BLO) test C and Z. The instructions CLC, CLV, CLZ, CLN, SEC, SEV, SEZ, SEN, CCC, SCC clear or set them directly.

Memory

The program sees a 64 KB address space of bytes. A word is two bytes, low byte at the even address, and must be at an even address: a word access at an odd address is an error (a trap through vector 4). A model with memory management maps these 64 KB, separately for instructions and data where the model allows it, onto a larger physical memory (18 bits on the 11/45, 22 bits on the 11/70). The disassembler shows the 16-bit addresses.

The top 8 KB, 160000 to 177777, is the I/O page: the device and processor registers, not memory. In the emulator core the console serial line (DL11) sits at 177560 to 177566 (receive status, receive buffer, transmit status, transmit buffer); a program on RT-11 or UNIX reads and writes these addresses directly.

The first words of memory are the trap vectors (below). Everything else is the program’s: a UNIX process starts at address 0 (the a.out text segment), an RT-11 program at the start address kept in word 40 of its memory image.

Trap and interrupt vectors

A trap or an interrupt pushes the PSW and then the PC on the stack and loads a new PC and PSW from a two-word vector in low memory. The vectors the instruction set uses (as the emulator core in the explorer’s checks takes them):

Vector	Cause
`4`	bus error: a word access at an odd address, a nonexistent location, a stack overflow; an addressing mode that has no address (`jmp r0`); and the double trap
`10`	reserved instruction: a word with no instruction (or an instruction the model lacks); also HALT and RESET are not reserved but privileged: a user-mode HALT traps through `4`
`14`	BPT and the trace trap (the T bit)
`20`	IOT
`30`	EMT (the RT-11 system calls)
`34`	TRAP (the UNIX system calls)
`244`	floating-point exception (FP11)
`250`	memory-management fault (not covered)

Not described

Known, not yet covered

The memory-management registers (PAR, PDR, MMR0 to MMR3), the stack limit register, the unibus map and the error registers; the vectors of devices.

Unknown

Which of the PSW bits and I/O-page addresses differ on models other than the 11/70 (the LSI-11, the T-11 and the J-11 have their own details that were not read).

PDP-11 Instruction Set – Registers, PSW and memory