PDP-11 Instruction Set – Floating point

Introduction

Two floating-point options existed. The FIS (also called the KEV11 on the LSI-11) is four instructions that work on numbers held on the stack. The FP11 is a separate floating-point processor with its own registers and instructions in the 17xxxx range, used by the 11/45, the 11/70 and later models; it is what UNIX and the Fortran and C compilers of those machines used. The disassembler decodes both and marks them with their feature group (fis, fpp).

The FP11 registers

Six 64-bit accumulators ac0 to ac5, a 16-bit status register FPS, an error code FEC and an error address FEA (the address of the instruction that failed). An instruction’s own accumulator field is two bits, so it names only ac0 to ac3; but a floating-point operand in addressing mode 0 names a register number 0 to 5 as an accumulator (ac4 and ac5 are reachable only that way). Mode 0 with register 6 or 7 is an error. The UNIX assembler writes the accumulators fr0 to fr3.

The mode bits (FD, FL) decide how many bytes a memory operand has, so the stepping of an autoincrement register (4 or 8 bytes for a floating operand, 2 or 4 for an integer one) depends on them; the instruction’s length does not, so the disassembler needs no mode to decode and does not track SETD and SETF.

Formats

• F (floating, 32 bits, two words): the first word has the sign in bit 15, an 8-bit exponent in bits 14–7 (excess 128) and the top 7 fraction bits; the second word has the other 16 fraction bits. The fraction has a hidden leading 1, so the value is ±0.1fff… (binary) × 2^{exponent−128}.
• D (double, 64 bits, four words): the same with 55 fraction bits.
• Zero is exponent 0 with sign 0. Sign 1 with exponent 0 is the undefined variable (“−0”): it is not a number, and reading it can trap.
• I and L integers are 16 and 32 bits, twos complement; the 32-bit one has its high word first.
• Immediate: a floating-point operand written with # (autoincrement of the PC) is one word, whatever the mode: the sign, exponent and top 7 fraction bits, with the rest of the number zero. So ldf #40200,ac0 loads 1.0 (040200) and the instruction is two words long. The emulator core used for the explorer’s checks does exactly this, and says it is peculiar to the hardware; the same one word is used for an integer immediate in L mode.

Errors

A floating-point error sets FER and stores a code in FEC; unless FID is set, the processor then traps through vector 244 before the next instruction. The codes (as in the emulator core): 2 illegal op code, 4 divide by zero, 6 conversion error, 8 overflow, 10 underflow, 12 undefined variable, 14 maintenance trap.

FP11 instructions

fsrc and fdst are a floating operand (mode 0 is an accumulator), src and dst an integer one, ac the instruction’s own accumulator (ac0 to ac3). The opcode is 17 with the number below; the accumulator takes bits 7–6 and the operand bits 5–0. Unless noted, the condition codes set are the floating FN FZ FV FC. The UNIX assembler’s name is in the second column where it differs.

Everything in 170003–170010 and 170013–170077 is reserved. (The emulator core executes these as no-operations; the decoder shows them as reserved.)

The FIS instructions

The FIS (11/35 and 11/40 option, and the LSI-11’s KEV11) works on 32-bit F numbers on the stack. The register R in the opcode points at the stack: the instruction takes two operands from it, replaces them with the result, and moves R up by 4. The emulator core in the explorer’s checks has no FIS, so these four are checked only against the tables.

Not described

Known, not yet covered

• The rounding rules, the exact flag changes of each instruction, the maintenance mode, and the operand order of the FIS’s stack arguments.

Unknown

• Which operand a FIS instruction takes first and the flags it sets: from names only.

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