DOL file format: hardware registers

Introduction

A GameCube or Wii program controls the graphics, video, audio, disc, controllers and memory cards by reading and writing registers that appear in the address space from 0xCC000000. Console code builds such an address with lis (the upper half) and ori, addi or a load or store displacement (the lower half). When the explorer sees that pair of instructions it adds a note with the register’s name. The block addresses and the registers below come from YAGCD chapter 5 and, for the Wii’s Hollywood chip, WiiBrew, read through page summaries (our words); the labels are the pages’ names written as identifiers, not a vendor’s header.

Register blocks

Base	Size	Block	What it is
`0xCC000000`	`0x80`	CP	Command Processor: the graphics FIFO.
`0xCC001000`	`0x100`	PE	Pixel Engine.
`0xCC002000`	`0x100`	VI	Video Interface.
`0xCC003000`	`0x100`	PI	Processor Interface: interrupts and the CPU FIFO.
`0xCC004000`	`0x80`	MI	Memory Interface: memory protection.
`0xCC005000`	`0x200`	DSP	Digital Signal Processor interface, with the ARAM DMA and the audio DMA.
`0xCC006000`	`0x40`	DI	DVD Interface.
`0xCC006400`	`0x100`	SI	Serial Interface: the controllers.
`0xCC006800`	`0x40`	EXI	External Interface: memory cards, the real-time clock and others.
`0xCC006C00`	`0x20`	AI	Audio Interface: audio streaming.
`0xCC008000`	4	GX FIFO	The port the CPU writes graphics commands to (any access size).

The EXI and AI register lists were not read, so those two blocks are named as blocks only (an access is noted as “EXI + 0x10”).

CP and PE

Address	Label	Meaning
`0xCC000000`	CP_SR	Status: GP idle flags, FIFO overflow and underflow, BP interrupt.
`0xCC000002`	CP_CR	Control: link and FIFO enables, interrupt enables.
`0xCC000004`	CP_CLEAR	Write 1 to clear the FIFO underflow and overflow flags.
`0xCC00000E`	CP_TOKEN	Token value.
`0xCC000010` to `0xCC000016`	CP_BBOX_LEFT, _RIGHT, _TOP, _BOTTOM	The bounding box.
`0xCC000020` to `0xCC00003E`	CP_FIFO_BASE, _END, _HIGH, _LOW, _DIST, _WRITE, _READ, _BP (each _LO then _HI, 16 bits)	The graphics FIFO: base and end addresses, watermarks, read/write distance, pointers and the breakpoint address.
`0xCC001000`	PE_ZCONF	Z configuration: update, compare function, compare enable.
`0xCC001002`	PE_ALPHA_CONF	Alpha configuration: blend operators, colour and alpha update, dither.
`0xCC001004`	PE_DST_ALPHA	Destination alpha: enable and value.
`0xCC001006`	PE_ALPHA_MODE	Alpha mode and threshold.
`0xCC001008`	PE_ALPHA_READ	Alpha read mode.
`0xCC00100A`	PE_ISR	Interrupt status: finish and token.
`0xCC00100E`	PE_TOKEN	The last token value.

VI, PI and MI

Address	Label	Meaning
`0xCC002000`	VI_VTR	Vertical timing.
`0xCC002002`	VI_DCR	Display configuration.
`0xCC002004`, `0xCC002008`	VI_HTR0, VI_HTR1	Horizontal timing.
`0xCC00200C`, `0xCC002010`	VI_VTO, VI_VTE	Odd and even field vertical timing.
`0xCC002014`, `0xCC002018`	VI_BBEI, VI_BBOI	Burst blanking intervals.
`0xCC00201C` to `0xCC002028`	VI_TFBL, VI_TFBR, VI_BFBL, VI_BFBR	Top and bottom field framebuffer addresses, left and right.
`0xCC00202C`, `0xCC00202E`	VI_DPV, VI_DPH	Current vertical and horizontal position.
`0xCC002030` to `0xCC00203C`	VI_DI0 to VI_DI3	Display interrupts.
`0xCC002040`, `0xCC002044`	VI_DL0, VI_DL1	Display latches.
`0xCC002048`, `0xCC00204A`	VI_HSW, VI_HSR	Scaling width and horizontal scaling.
`0xCC00204C` to `0xCC002064`	VI_FCT0 to VI_FCT6	Filter coefficient tables.
`0xCC00206C`, `0xCC00206E`	VI_VICLK, VI_VISEL	Video clock select; DTV status.
`0xCC002072`, `0xCC002074`	VI_HBE, VI_HBS	Border end and start.
`0xCC003000`	PI_INTSR	Interrupt cause.
`0xCC003004`	PI_INTMR	Interrupt mask.
`0xCC00300C`, `0xCC003010`, `0xCC003014`	PI_FIFO_BASE, PI_FIFO_END, PI_FIFO_WRITE	The CPU FIFO (YAGCD marks the second and third names as uncertain).
`0xCC003024`	PI_RESET	Writing here appears to reset the console.
`0xCC00302C`	PI_CONSOLE_TYPE	Console type in bits 28 to 31.
`0xCC004000` to `0xCC00400C`	MI_PROT_REGION1 to 4	Protected regions.
`0xCC004010`	MI_PROT_TYPE	Type of protection (4 channels of 2 bits).
`0xCC00401C`, `0xCC00401E`	MI_INT_MASK, MI_INT_CAUSE	Interrupt mask and cause.
`0xCC004022`, `0xCC004024`	MI_ADDR_LO, MI_ADDR_HI	The address that failed protection.

DSP, DI and SI

Address	Label	Meaning
`0xCC005000` to `0xCC005006`	DSP_MAIL_TO_DSP_H, _L; DSP_MAIL_FROM_DSP_H, _L	The mailboxes between the CPU and the DSP.
`0xCC00500A`	DSP_CSR	DSP control and status: reset, halt, interrupts and masks.
`0xCC005012`, `0xCC005016`, `0xCC00501A`	AR_SIZE, AR_MODE, AR_REFRESH	ARAM size, mode and refresh.
`0xCC005020` to `0xCC00502A`	AR_DMA_MMADDR, AR_DMA_ARADDR, AR_DMA_CNT (each _H then _L)	ARAM DMA: main memory address, ARAM address, direction bit and length.
`0xCC005030`, `0xCC005032`	AI_DMA_START_H, _L	Audio DMA start address.
`0xCC005036`	AI_DMA_CONTROL	Audio DMA play bit and length in 32-byte units.
`0xCC00503A`	AI_DMA_BYTES_LEFT	Audio DMA bytes left.
`0xCC006000`	DI_SR	Status: break, transfer complete and device error interrupts and masks.
`0xCC006004`	DI_CVR	Cover status and cover interrupt.
`0xCC006008` to `0xCC006010`	DI_CMDBUF0 to DI_CMDBUF2	Command and subcommand bytes; offset in 32-bit words; source length.
`0xCC006014`, `0xCC006018`	DI_MAR, DI_LENGTH	DMA memory address and length (32-byte aligned).
`0xCC00601C`	DI_CR	Control: access mode, DMA or immediate mode, start.
`0xCC006020`, `0xCC006024`	DI_IMMBUF, DI_CFG	Immediate data buffer; configuration latched at reset.
`0xCC006400` to `0xCC006424`	SI_C0_OUTBUF … SI_C3_OUTBUF with _INBUF_H and _INBUF_L	The four controller channels: output command and two input words each (12 registers).
`0xCC006430`	SI_POLL	Polling control: enables, interval, vertical blank copy.
`0xCC006434`	SI_COMCSR	Communication control and status.
`0xCC006438`	SI_SR	Status and error flags per channel.
`0xCC00643C`	SI_EXILK	Locks the EXI clock from being set to 32 MHz.
`0xCC006480`	SI_IOBUF	The 128-byte i/o buffer.

Hollywood (Wii)

WiiBrew gives the Hollywood registers at physical 0x0D800000, which the CPU reaches at 0xCD800000.

Address	Label	Meaning
`0xCD800000`, `0xCD800004`	HW_IPC_PPCMSG, HW_IPC_PPCCTRL	Inter-processor messages: message and control.
`0xCD800010`	HW_TIMER	The Starlet timer.
`0xCD800030`, `0xCD800034`	HW_PPCIRQFLAG, HW_PPCIRQMASK	Interrupt flags and mask for the PowerPC.
`0xCD800060`	HW_SRNPROT	SRAM visibility and bus control.
`0xCD800064`	HW_AHBPROT	PowerPC access control for the AHB devices.
`0xCD800070`	HW_AIPPROT	EXI enable and control for the PowerPC.
`0xCD8000C0`, `0xCD8000E0`	HW_GPIOB_OUT, HW_GPIO_OUT	The starts of the GPIOB and GPIO blocks.
`0xCD800100`	HW_ARB_CFG_M0	AHB arbitration configuration.
`0xCD800180`	HW_COMPAT	DI and boot-related flags.
`0xCD800190`, `0xCD800194`	HW_CLOCKS, HW_RESETS	Clock control and subsystem resets.
`0xCD800214`	HW_VERSION	Hollywood hardware revision.

The same page also lists a register block at 0x0D000000 (length 0x400) that it describes as a mirror base; the explorer names an access inside 0xCD000000 to 0xCD008000 as “Hollywood” without a register.

Not described

Known, not yet covered

Reference: the bit fields of every register, the EXI and AI register lists, the internal CP, XF and BP registers of the graphics chip (written through the GX FIFO), the DSP’s internal registers and the rest of the Hollywood registers.
Viewer: a register is named only where an address built by lis and ori, addi or a displacement is found within 16 instructions; an address held in a register across a call is not followed.

Unknown

YAGCD marks two PI FIFO register names as uncertain; the viewer repeats them as printed.

DOL File Format – Hardware Registers