Spellings the decoder uses
The option “Pseudo-instructions” (on by default) chooses between the short spelling and the encoded one. With it off the decoder writes the instruction as the instruction set defines it; with it on, as LLVM writes it.
| Written (on) | Encoded as (off) | Where |
|---|---|---|
push {r4, lr} | stmdb sp!, {r4, lr} | A32 (also a single register: str r0, [sp, #-4]! stays as it is), T16 (its own encoding), T32 (push.w) |
pop {r4, pc} | ldm sp!, {r4, pc} (ldmia) | A32, T16, T32 (pop.w) |
vpush {d8, d9}, vpop {d8, d9} | vstmdb sp!, …, vldmia sp!, … | VFP |
lsl r0, r1, #2, lsr, asr, ror | mov r0, r1, lsl #2 | A32 data processing; in T32 lsl.w is mov.w with a shifted register |
lsl r0, r1, r2 | mov r0, r1, lsl r2 | A32 |
rrx r0, r1 | mov r0, r1, rrx (the shifter operand ROR with an amount of 0) | A32, T32 |
mov r0, r1 | mov r0, r1, lsl #0 | A32, T32 (mov.w); in T16 movs r0, r1 is lsls r0, r1, #0 outside an IT block |
nop | mov r0, r0 or hint #0; in Thumb nop is 0xBF00, and mov r8, r8 (0x46C0) stays mov | The hint encoding is the architectural nop (ARMv6K, ARMv6T2) |
rsbs r0, r1, #0 (T16 negs in GNU) | The same encoding; LLVM writes rsbs | T16 |
add r0, sp, r0 | the T16 add Rdn, Rm with Rm = sp | T16: three registers are written when Rm is sp |
adr r0, 0x8004 | T16 and T32 add Rd, pc, #imm or sub Rd, pc, #imm (addw, subw) | Thumb only: in A32 the decoder keeps add and sub with the PC (as LLVM does) and shows the address it refers to |
bx lr, pop {…, pc} | (not aliases: marked as the flow return in the listing) | – |
cmp, cmn, tst, teq | The data-processing instruction with S set and no destination register (Rd = 0 in A32, Rd = 1111 in T32) | A32, T32 |
GNU objdump differs in a few spellings (negs, stmia and ldmia in Thumb, nop for mov r8, r8, movs.w r1, r2, lsr #2 for lsrs.w r1, r2, #2, cs and cc for hs and lo, coprocessor operands as 15, 0, r3, cr13, cr0, {3}); the comparison tests bring both to one form before comparing.