The address space
The CPU address space is decoded by bits 26 to 24; the top five bits are ignored, so each region repeats through its 16 MiB window. Region 7 is the cartridge ROM, mirrored through the whole window: addresses are masked with rom_size − 1 (Sacred Tech Scroll; Beetle VB’s loader maps the ROM at 7 << 24 in steps of its size, and mirrors a ROM smaller than 64 KiB up to 64 KiB). Region 4 (0x04000000–0x04FFFFFF) is the cartridge expansion, used by no commercial game; it can raise the cartridge interrupt (exception code 0xFE20). Region 3 is not used. Addresses 0x08000000 and above repeat the whole map.
| Range | Name | What is there |
|---|---|---|
0x00000000–0x0007FFFF | VIP | Video: frame buffers, characters, background maps, world and object attributes (RAM below 0x00040000) and the VIP registers at 0x0005F800 |
0x01000000–0x010007FF | VSU | Sound: waveform RAM, modulation RAM and the channel registers |
0x02000000–0x02000028 | Hardware control | Link port, game pad, timer and wait control (below) |
0x05000000–0x0500FFFF | WRAM | Work RAM, 64 KiB |
0x06000000–0x06FFFFFF | Cartridge RAM | RAM on the cartridge, possibly battery-backed; a power of two up to 16 MiB, mirrored through the window; absent on many cartridges. The ROM image does not say how much RAM there is (the emulators.org core has 8 KiB, Beetle VB maps 64 KiB) |
0x07000000–0x07FFFFFF | Cartridge ROM | The ROM, up to 16 MiB; its last byte is 0x07FFFFFF, also seen as 0xFFFFFFFF |
Hardware control registers
Named in the disassembly. The addresses are checked against the raw text of the Sacred Tech Scroll, which names them: 0x02000000 Link Control Register, 0x02000004 Auxiliary Link Register, 0x02000008 Link Transmit Data, 0x0200000C Link Receive Data, 0x02000010 Game Pad Input Low, 0x02000014 Game Pad Input High, 0x02000018 and 0x0200001C Timer Counter/Reload Low and High, 0x02000020 Timer Control Register, 0x02000024 Wait Control Register, 0x02000028 Game Pad Input Control Register. The short names in the table (CCR, SDLR …) are the community’s abbreviations, not the Scroll’s; the meanings are brief. Other addresses in 0x02000000–0x02FFFFFF are not registers.
| Address | Name | Meaning |
|---|---|---|
0x02000000 | CCR | Communication control (link port) |
0x02000004 | CCSR | Communication clock/status (link port) |
0x02000008 | CDTR | Communication transmit data |
0x0200000C | CDRR | Communication receive data |
0x02000010 | SDLR | Game pad data, low byte |
0x02000014 | SDHR | Game pad data, high byte |
0x02000018 | TLR | Timer counter, low byte |
0x0200001C | THR | Timer counter, high byte |
0x02000020 | TCR | Timer control |
0x02000024 | WCR | Wait control (ROM and RAM access times) |
0x02000028 | SCR | Game pad control |
The emulators.org core reads the game pad as SDLR (low byte) and SDHR (high byte) with the bits A 0x0004, B 0x0008, right trigger 0x0010, left trigger 0x0020, and so on; the bit assignment is not used by the viewer.
VIP registers and memory
| Address | Name | Meaning |
|---|---|---|
0x0005F800 | INTPND | Interrupt pending |
0x0005F802 | INTENB | Interrupt enable |
0x0005F804 | INTCLR | Interrupt clear |
0x0005F820 | DPSTTS | Display status (read) |
0x0005F822 | DPCTRL | Display control (write) |
0x0005F824 | BRTA | LED brightness A |
0x0005F826 | BRTB | LED brightness B |
0x0005F828 | BRTC | LED brightness C |
0x0005F82A | REST | LED rest period |
0x0005F82E | FRMCYC | Frame cycle |
0x0005F830 | CTA | Column table address |
0x0005F840 | XPSTTS | Drawing status (read) |
0x0005F842 | XPCTRL | Drawing control (write) |
0x0005F844 | VER | VIP version |
0x0005F848–0x0005F84E | SPT0–SPT3 | Object group pointers |
0x0005F860–0x0005F866 | GPLT0–GPLT3 | Background palettes |
0x0005F868–0x0005F86E | JPLT0–JPLT3 | Object palettes |
0x0005F870 | BKCOL | Background colour |
The viewer labels each of the 27 registers (the groups above are four registers each). The layout of the video RAM (frame buffers at 0x00000000, 0x00008000, 0x00010000 and 0x00018000, character tables in the gaps, background maps from 0x00020000, window attributes (“worlds”) at 0x0003D800–0x0003DBFF, the column table at 0x0003DC00–0x0003DFFF (left half to 0x0003DDFF, right half from 0x0003DE00), objects at 0x0003E000–0x0003FFFF) and the register addresses above agree with the Sacred Tech Scroll’s tables (“VIP Memory Map”); the Scroll calls REST “LED Brightness Idle”, FRMCYC “Frame Repeat”, BKCOL “Clear Color” and the palettes “BG” and “OBJ”. The bit fields of the registers are not described here.
Not described
See the overview: the VIP and VSU contents are not decoded and the register meanings are brief.