The processor of the Master System, Game Gear and SG-1000 is a Zilog Z80, running at about
3.58 MHz. It addresses 64 KB: the cartridge answers in 0x0000–0xBFFF and the console’s own RAM sits
above. The explorer names the mapper registers and the ports in the disassembly (ports).
The map follows SMS Power’s memory map page.
Address space
| Range | What is there |
|---|---|
0x0000–0x03FF | ROM, never remapped by the Sega mapper (the start of page 0, so the vectors below stay in place) |
0x0400–0x3FFF | ROM, slot 0: the rest of the 16 KB page chosen by the slot 0 register |
0x4000–0x7FFF | ROM, slot 1 |
0x8000–0xBFFF | ROM or cartridge RAM, slot 2 |
0xC000–0xDFFF | System RAM, 8 KB |
0xE000–0xFFFF | System RAM again (a mirror) |
0xFFF8–0xFFFB | 3-D glasses control (in the mirror; not described here) |
0xFFFC–0xFFFF | Sega mapper registers, in the mirror: a write goes to the register and to RAM, a read returns RAM only |
The Game Gear has the same map; SMS Power gives no separate Game Gear table. The SG-1000 and SC-3000 have cartridge space at
0x0000–0xBFFF and RAM above, but SMS Power’s pages do not give their RAM size, so it is not stated here.
Reset, restarts and interrupts
The Z80 starts at 0x0000. The restart instructions jump to multiples of 8, and the two interrupts go to fixed
addresses. Since RST $38 is the byte 0xFF and unused ROM is often filled with it, a stray jump into
blank space runs the interrupt handler again and again.
| Address | Name in the viewer | What |
|---|---|---|
0x0000 | reset | Where the Z80 starts after a reset (also RST $00). Usually di, im 1 and a jump to the program. |
0x0008, 0x0010, 0x0018, 0x0020, 0x0028, 0x0030 | rst_08 … rst_30 | Targets of RST $08 to RST $30, a one-byte call. |
0x0038 | irq | The maskable interrupt in interrupt mode 1, where the Z80 goes when /INT is raised and interrupts are enabled; also RST $38. |
0x0066 | nmi | The non-maskable interrupt, which the Z80 takes on a falling edge of /NMI. On the Master System it is the Pause button. |
The viewer’s first-instruction table decodes these addresses. Which VDP events raise the maskable interrupt, and how the
Game Gear’s Start button relates to the NMI, are not in the sources read; the Game Gear’s Start button is read at port
0x00. That the NMI is the Master System’s Pause button follows JSSMS, whose z80.js raises it from the pause key,
and the common documentation.
Sources
- Memory Map – SMS Power
- Interrupt Vectors and Interrupt Mechanism – SMS Power: the Z80’s own behaviour
Not described
The 3-D glasses registers, cartridge RAM size, the SG-1000 and SC-3000 RAM, and the interrupt sources (the VDP’s frame and line interrupts) are not covered.