Several iNES mapper numbers were under-specified: one number covers boards that behave differently. NES 2.0 adds a 4-bit submapper number (byte 8, bits 4–7) to tell them apart. Submapper 0 is the default iNES behaviour, so that existing files stay compatible; the other values are defined per mapper on the NESdev Wiki’s submapper page, and this page lists every one it gives.
Mapper numbering
The mapper number is 12 bits: bits 0–3 from byte 6 (upper nibble), bits 4–7 from byte 7 (upper nibble) and bits 8–11 from byte 8 (lower nibble), 0 to 4095. Numbers 0 to 255 are the iNES numbers. The NESdev Wiki’s mapper grid lists the higher numbers assigned so far (up to the 700s), each with its own page.
Some mappers once had submappers that are now deprecated, because the board was given a mapper number of its own; a file should use that number instead.
Defined submappers
| Mapper | Sub | Meaning |
|---|---|---|
| 1 (MMC1) | 0 | Normal behaviour. |
| 1 | Deprecated: SUROM-style extra PRG banking (same as 0). | |
| 2 | Deprecated: SOROM-style extra PRG banking (same as 0). | |
| 3 | Deprecated: MMC1A; use mapper 155. | |
| 4 | Deprecated: SXROM-style extra PRG banking (same as 0). | |
| 5 | Fixed 32 KiB PRG ROM, no PRG banking (SEROM, SHROM, SH1ROM). | |
| 6 | 2ME: Famicom Network System MMC1B variant with EEPROM storage. | |
| 2 (UxROM) | 0 | Bus conflict behaviour unspecified. |
| 1 | No bus conflicts. | |
| 2 | Bus conflicts: the written value is ANDed with the ROM value. | |
| 3 (CNROM) | 0 | Bus conflict behaviour unspecified. |
| 1 | No bus conflicts. | |
| 2 | Bus conflicts, ANDed. | |
| 4 (MMC3) | 0 | Sharp MMC3, standard behaviour. |
| 1 | MMC6, with its own PRG RAM enable scheme. | |
| 2 | MMC3C with hard-wired mirroring (no known licensed games). | |
| 3 | MC-ACC. | |
| 4 | NEC MMC3: loading latch 0 disables the IRQ. | |
| 5 | Includes a T9552 scrambling chip. | |
| 7 (AxROM) | 0 | Bus conflict behaviour unspecified. |
| 1 | No bus conflicts. | |
| 2 | Bus conflicts, ANDed. | |
| 16 (Bandai FCG) | 0 | Unspecified: emulate both FCG-1/2 and LZ93D50. |
| 1 | Deprecated: LZ93D50 with 128-byte EEPROM; use mapper 159. | |
| 2 | Deprecated: Datach system; use mapper 157. | |
| 3 | Deprecated: 8 KiB WRAM instead of EEPROM; use mapper 153. | |
| 4 | FCG-1/2: registers only at $6000–$7FFF, IRQ counter not latched. | |
| 5 | LZ93D50 with no or a 256-byte EEPROM: registers only at $8000–$FFFF, latched IRQ counter. | |
| 19 (Namco 163) | 0 | Default; expansion sound volume unspecified. |
| 1 | Deprecated: internal RAM battery-backed, no external PRG RAM. | |
| 2 | No expansion sound. | |
| 3 | Expansion sound about 11–13 dB louder than the APU. | |
| 4 | Expansion sound about 16–17 dB louder than the APU. | |
| 5 | Expansion sound about 18–19.5 dB louder than the APU. | |
| 21 (VRC4) | 0 | Default: responds to both VRC4 address schemes. |
| 1 | VRC4a addressing. | |
| 2 | VRC4c addressing. | |
| 23 (VRC2/VRC4) | 0 | Default: responds to several address schemes. |
| 1 | VRC4f, with VRC2b-style in-order addressing. | |
| 2 | VRC4e addressing. | |
| 3 | VRC2b, with a single bit of memory at $6000–$6FFF. | |
| 25 (VRC2/VRC4) | 0 | Default: responds to several address schemes. |
| 1 | VRC4b addressing. | |
| 2 | VRC4d addressing. | |
| 3 | VRC2c, with no VRC4-only features. | |
| 32 | 0 | Normal, mapper-controlled horizontal or vertical mirroring. |
| 1 | Major League: fixed one-screen mirroring and fixed PRG banking. | |
| 34 | 0 | Normal: BNROM and NINA-001 combined. |
| 1 | NINA-001 only. | |
| 2 | BNROM only. | |
| 68 | 0 | Normal, up to 256 KiB PRG. |
| 1 | Sunsoft Dual Cartridge System: up to 128 KiB PRG and a licensing chip. | |
| 71 (Camerica) | 0 | Hard-wired horizontal or vertical mirroring. |
| 1 | Fire Hawk: mapper-controlled single-screen mirroring. | |
| 78 | 0 | Unspecified. |
| 1 | Cosmo Carrier: single-screen mirroring. | |
| 2 | Deprecated: fixed vertical mirroring with WRAM. | |
| 3 | Holy Diver: mapper-controlled horizontal or vertical mirroring. | |
| 85 (VRC7) | 1 | VRC7b, registers selected with A3 (Tiny Toon Adventures). |
| 2 | VRC7a, registers selected with A4 (Lagrange Point). | |
| 91 | 0 | YY830624C/JY830848C (J.Y. Company clone board). |
| 1 | EJ-006-1 (the original Super Fighter III board). | |
| 114 | 0 | MMC3 with one fixed scrambling pattern (The Lion King, Aladdin). |
| 1 | A different scrambling pattern (Boogerman). | |
| 178 | 0 | No infrared sensor. |
| 1 | Gameinis infrared sensor present. | |
| 185 (CNROM with protection) | 0 | Correct value unknown; the NESdev page describes a heuristic. |
| 4 | CHR ROM enabled only when latch bits 0–1 are 0. | |
| 5 | CHR ROM enabled only when latch bits 0–1 are 1. | |
| 6 | CHR ROM enabled only when latch bits 0–1 are 2. | |
| 7 | CHR ROM enabled only when latch bits 0–1 are 3. | |
| 206 (Namco 118) | 0 | Namcot 118 with normal PRG banking. |
| 1 | Namcot 3407, 3417 and 3451 boards: unbanked 32 KiB PRG ROM. | |
| 210 (Namco 175/340) | 0 | Namco 175 or 340, decided from the header flags. |
| 1 | Namco 175: hard-wired mirroring, no IRQ. | |
| 2 | Namco 340: one-screen, horizontal or vertical mirroring; no IRQ or RAM. | |
| 215 | 0 | UNL-8237: two non-overlapping outer bank bits. |
| 1 | UNL-8237A: three overlapping outer bank bits. | |
| 232 (Quattro) | 0 | Normal. |
| 1 | Aladdin Deck Enhancer: outer bank bits swapped. | |
| 256 | 0 | Normal opcode and register addressing. |
| 1 | Waixing VT03 register addressing. | |
| 2 | Power Joy Supermax register addressing. | |
| 3 | Zechess/Hummer Team register addressing. | |
| 4 | Qishenglong register addressing. | |
| 5 | Waixing VT02 register addressing. | |
| 11 | Vibes: normal register addressing, switchable opcode bit swaps. | |
| 12 | Cheertone: switchable opcode bit swap (D7/D6, D1/D2). | |
| 13 | Taikee: switchable opcode bit swap (D1 and D4). | |
| 14 | Karaoto: switchable opcode bit swap (D6 and D7). | |
| 15 | Jungletac: switchable opcode bit swap (D5 and D6). | |
| 268 | 0 | Coolboy: outer bank registers at $6000–$6003. |
| 1 | Mindkids: outer bank registers at $5000–$5003. |
Mappers not in the table have no submappers on the NESdev submapper page; for them only submapper 0 is defined there.
Sources
- NES 2.0 submappers – NESdev Wiki: every submapper in the table
- NES 2.0 – NESdev Wiki: where the mapper and submapper bits sit
- Mapper – NESdev Wiki: the grid of assigned mapper numbers