The processor sees 32 KiB of ROM, but a cartridge can hold up to 8 MiB. A memory bank controller (MBC) on the
cartridge decides which 16 KiB bank appears at $4000–$7FFF. The program talks to it by
writing to the ROM area: ROM cannot be written, so the write goes to the controller. The
cartridge type in the header says which controller is fitted. Every register is
write-only. The tables below are from Pan Docs; the viewer shows the same table for the controller named in the header.
MBC1
| Write to | Register | Effect |
|---|---|---|
$0000–$1FFF | RAM enable | A $A in the low 4 bits enables the external RAM; any other value disables it. |
$2000–$3FFF | ROM bank number | 5 bits. Writing $00 selects bank $01; the test is on the whole 5-bit value, so on cartridges of 256 KiB or less setting bit 4 ($10) lets bank 0 appear at $4000. |
$4000–$5FFF | RAM bank / upper ROM bank | 2 bits: the RAM bank 0–3 on 32 KiB RAM cartridges, bits 5–6 of the ROM bank on cartridges of 1 MiB or more; otherwise no effect. |
$6000–$7FFF | Banking mode select | 1 bit. Mode 0 (default) keeps $0000–$3FFF on bank 0 and $A000–$BFFF on RAM bank 0; in mode 1 the 2-bit register switches those as well ($00/$20/$40/$60 at $0000 on large cartridges). |
At $4000 the bank is (2-bit register << 5) plus the 5-bit register. A multi-game variant (MBC1M) feeds the 2-bit
register into bits 4–5 instead and ignores the top bit of the 5-bit register.
MBC2
Registers at $0000–$3FFF; bit 8 of the address picks the function.
| Write to | Register | Effect |
|---|---|---|
| address bit 8 clear | RAM enable | A $A in the low 4 bits enables the RAM. Disabled at power-on. |
| address bit 8 set | ROM bank number | Low 4 bits, so banks 0–15 (256 KiB at most); 0 selects bank 1. Bank 1 at power-on. |
The RAM is 512 values of 4 bits built into the chip at $A000–$A1FF (only the low 4 bits of each byte are used),
repeated through $BFFF. A battery keeps it when the console is off.
MBC3
| Write to | Register | Effect |
|---|---|---|
$0000–$1FFF | RAM and timer enable | $0A enables RAM and clock access, $00 disables. |
$2000–$3FFF | ROM bank number | 7 bits; $00 selects bank $01. |
$4000–$5FFF | RAM bank / clock register select | $00–$07 a RAM bank; $08–$0C a clock register at $A000–$BFFF. |
$6000–$7FFF | Latch clock data | Writing $00 then $01 copies the time into the clock registers. |
Clock registers: $08 seconds (0–59), $09 minutes (0–59), $0A hours (0–23),
$0B low 8 bits of the day counter, $0C bit 0 day counter bit 8, bit 6 halt, bit 7 day carry.
MBC5
| Write to | Register | Effect |
|---|---|---|
$0000–$1FFF | RAM enable | $0A enables, $00 disables. |
$2000–$2FFF | ROM bank, low 8 bits | Bank 0 can be selected. |
$3000–$3FFF | ROM bank, ninth bit | Up to 512 banks (8 MiB). |
$4000–$5FFF | RAM bank | $00–$0F; on cartridges with a rumble motor, bit 3 drives it. |
MBC6
Used by one game, with an 8 Mbit flash chip besides ROM and RAM. Both ROM windows are 8 KiB.
| Write to | Register | Effect |
|---|---|---|
$0000–$03FF | RAM enable | $0A enables, $00 disables. |
$0400–$07FF | RAM bank A | Bank for $A000–$AFFF (4 KiB, banks 0–7). |
$0800–$0BFF | RAM bank B | Bank for $B000–$BFFF. |
$0C00–$0FFF | Flash enable | Bit 0. |
$1000 | Flash write enable | Bit 0; controls sector 0 and the hidden region. |
$2000–$27FF | ROM/flash bank A number | For $4000–$5FFF (8 KiB, banks 0–$7F). |
$2800–$2FFF | Bank A select | $00 ROM, $08 flash. |
$3000–$37FF | ROM/flash bank B number | For $6000–$7FFF. |
$3800–$3FFF | Bank B select | $00 ROM, $08 flash. |
MBC7
With a two-axis accelerometer and a 256-byte EEPROM.
| Write to | Register | Effect |
|---|---|---|
$0000–$1FFF | RAM enable 1 | $0A enables the RAM registers, $00 disables. |
$2000–$3FFF | ROM bank number | Selects the bank at $4000. |
$4000–$5FFF | RAM enable 2 | $40 enables access; both enables must be set. |
At $A000–$AFFF the address bits 4–7 pick a register: $Ax0x write $55 erases the accelerometer
latch; $Ax1x write $AA latches it; $Ax2x/$Ax3x read the X value (low, high),
$Ax4x/$Ax5x the Y value (before the first latch both read $8000); $Ax8x is the EEPROM
(bit 0 DO, bit 1 DI, bit 6 CLK, bit 7 CS).
MMM01
For multi-game cartridges. It starts in an unmapped mode in which the last 32 KiB of the ROM (the menu) appear at
$0000–$7FFF; the menu sets the extended bits to choose a game, then sets mapping enable, which makes the chip
behave like an MBC1 for that game. The viewer shows the cartridge as the game will see it, not the menu’s start-up mapping.
| Write to | Register | Effect |
|---|---|---|
$0000–$1FFF | RAM enable, RAM bank mask, mapping enable | Bits 0–3 $A enable RAM; bits 4–5 mask the RAM bank bits; bit 6 turns on MBC1 behaviour and locks the extended bits. |
$2000–$3FFF | ROM bank number | Bits 0–4 as MBC1 (maskable); bits 5–6 the middle bits, usable only before mapping. |
$4000–$5FFF | RAM bank number | Bits 0–1 the RAM bank; bits 2–3 RAM bank high and bits 4–5 ROM bank high (only before mapping); bit 6 locks the mode select. |
$6000–$7FFF | Banking mode select | Bit 0 the MBC1 mode; bits 1–5 the ROM bank mask; bit 6 multiplex. |
HuC1 and HuC3
Hudson Soft’s controllers add an infrared port; the HuC3 adds a real-time clock.
| Write to | HuC1 | HuC3 |
|---|---|---|
$0000–$1FFF | $0E selects infrared mode, anything else RAM mode. | Low 4 bits: $0 RAM read-only, $A RAM read/write, $B RTC command write, $C RTC response read, $D RTC semaphore, $E infrared. |
$2000–$3FFF | ROM bank, at least 6 bits. | ROM bank, 7 bits. |
$4000–$5FFF | RAM bank, at least 2 bits. | RAM bank, at least 2 bits. |
$6000–$7FFF | No effect. | Unused (games write $01 with no visible effect). |
HuC1 at $A000–$BFFF in infrared mode: write $01 to turn the transmitter on, $00 off;
a read gives $C1 if light was seen, $C0 if not.
Game Boy Camera
Works much like an MBC3.
| Write to | Register | Effect |
|---|---|---|
$0000–$1FFF | RAM enable | $0A enables writes, $00 disables. Disabled at reset. |
$2000–$3FFF | ROM bank number | $00–$3F; bank 1 at reset. |
$4000–$5FFF | RAM bank / camera register select | $00–$0F a RAM bank; a value with bit 4 set (usually $10) selects the camera registers, mirrored every $80 bytes. |
TAMA5
Bandai’s controller (cartridge type $FD). Pan Docs does not describe its registers, so none are listed here and the viewer
assumes a 16 KiB window at $4000.
Sources
Not described
The TAMA5’s registers; the MBC6 flash commands; the MBC7 EEPROM command set; the HuC3 real-time-clock commands; and the exact power-on mapping of each controller beyond what is stated above.