Introduction
The 6507 can address 8 KiB, and the cartridge gets 4 KiB of that, $1000-$1FFF. A bigger ROM is cut into
banks and the cartridge shows one at a time. The program switches by touching a hotspot: reading or
writing an address that the cartridge decodes (most schemes use the top of the window, $1FF4-$1FFB and
near). Nothing in the file says which scheme a ROM uses, so the explorer offers it as a choice. The default depends on the
size only:
| Size | Default | Other schemes of that size |
|---|---|---|
| under 2 KiB, 2 KiB | 2K | CV |
| 4 KiB | 4K | |
| 8 KiB | F8 | E0, 3F, FE, UA, 0840 |
| 12 KiB | FA | |
| 16 KiB | F6 | E7 |
| 32 KiB | F4 | 3E |
| 64 KiB | F0 | EF |
| 10240 to 10496 bytes | DPC | |
| a multiple of 8448 bytes | AR (Supercharger) |
These sizes are the ones the 6502.ts emulator sorts its detection by; it then looks at the code (for example for a
STA $1FF9 to tell F8 from the others) and this site does not. A ROM of any other size is shown as 4 KiB banks
one after the other, with no switching described.
Schemes
Hotspot addresses are the 13-bit addresses the 6507 puts out ($1FF8); a program written for $F000
names the same place $FFF8. The checked mark means the numbers were read from the code of the 6502.ts
core in emulators.org/emulator/6502-ts (its cartridge classes) and compared in the page test; the others come
from general knowledge only.
| Scheme | Size | Banks | Hotspots | Start bank | Checked |
|---|---|---|---|---|---|
| 2K | 2 KiB | 1 | none | 0 | yes |
| 4K | 4 KiB | 1 | none | 0 | yes |
| F8 | 8 KiB | 2 of 4 KiB | $1FF8, $1FF9 | 1 | yes |
| FA | 12 KiB | 3 of 4 KiB | $1FF8 to $1FFA | 0 | yes |
| F6 | 16 KiB | 4 of 4 KiB | $1FF6 to $1FF9 | 0 | yes |
| F4 | 32 KiB | 8 of 4 KiB | $1FF4 to $1FFB | 0 | yes |
| F0 | 64 KiB | 16 of 4 KiB | $1FF0 (next bank) | 0 | yes |
| EF | 64 KiB | 16 of 4 KiB | $1FE0 to $1FEF | 15 | yes |
| E0 | 8 KiB | 8 of 1 KiB | $1FE0 to $1FF7 | 7 (all slices) | yes |
| E7 | 16 KiB | 8 of 2 KiB | $1FE0 to $1FEB | 0 | yes |
| 3F | 8 KiB and up | 2 KiB banks | write $003F | 0 | yes |
| 3E | 32 KiB and up | 2 KiB banks, RAM | write $003E, $003F | 0 | yes |
| FE | 8 KiB | 2 of 4 KiB | access to $01FE | 0 | yes |
| UA | 8 KiB | 2 of 4 KiB | $0220, $0240 | 0 | yes |
| 0840 | 8 KiB | 2 of 4 KiB | $0800, $0840 | 0 | yes |
| CV | 2 KiB + RAM | 1 | none | 0 | no |
| DPC | 8 KiB + 2 KiB | 2 of 4 KiB | $1FF8, $1FF9 | 1 | no |
| AR | n x 8448 bytes | loads | BIOS | n/a | no |
2K
No bank switching. The 2 KiB ROM appears at $1000-$17FF and again at $1800-$1FFF (one address
line is not connected). The vectors are at the end of the file. A ROM smaller than 2 KiB is treated the same way.
4K
No bank switching: the ROM fills $1000-$1FFF. The vectors are the last six bytes of the file.
F8
8 KiB, two 4 KiB banks. Touching $1FF8 selects bank 0, $1FF9 selects bank 1. The 6502.ts core starts
in bank 1 (the real chip starts in either). Carts of this kind may add the SuperChip.
FA (CBS RAM Plus)
12 KiB, three 4 KiB banks, selected by $1FF8, $1FF9 and $1FFA. 256 bytes of RAM sit at the
start of the window: the write port is $1000-$10FF and the read port $1100-$11FF. Start bank 0.
F6
16 KiB, four 4 KiB banks, selected by $1FF6 to $1FF9 (bank 0 to 3). Start bank 0. SuperChip possible.
F4
32 KiB, eight 4 KiB banks, selected by $1FF4 to $1FFB (bank 0 to 7). Start bank 0. SuperChip possible.
F0 (Megaboy)
64 KiB, sixteen 4 KiB banks. There is a single hotspot, $1FF0: touching it moves on to the next bank (after bank 15
comes bank 0). The core starts in bank 0. Because every touch advances the bank, a disassembly cannot say which bank an address
belongs to without knowing how many times the program touched it.
EF
64 KiB, sixteen 4 KiB banks, selected by $1FE0 to $1FEF (bank 0 to 15). The core starts in bank 15. The
6502.ts detection takes a 64 KiB ROM as EF when its last bytes spell efef or efsc or the code touches those hotspots;
this site cannot see that from the file and offers F0 by default.
E0 (Parker Brothers)
8 KiB as eight 1 KiB banks. The window is four 1 KiB slices. The last slice, $1C00-$1FFF, is always bank 7. The first
three show any bank: $1FE0-$1FE7 choose the bank in $1000-$13FF, $1FE8-$1FEF in $1400-$17FF
and $1FF0-$1FF7 in $1800-$1BFF (the low three bits of the address are the bank number). At start all four slices show
bank 7. The explorer lists the eight banks and disassembles each at the start of the window.
E7 (M-Network)
16 KiB as eight 2 KiB banks, with RAM. The lower half of the window, $1000-$17FF, shows bank 0 to 6 (hotspots
$1FE0-$1FE6) or 1 KiB of RAM ($1FE7; write port $1000-$13FF, read port $1400-$17FF as the
usual description says). The upper half, $1800-$1FFF, is bank 7 always, with its first 256 bytes replaced by one of four
RAM banks ($1FE8-$1FEB). The vectors are in bank 7.
3F (Tigervision)
2 KiB banks. A write to $003F, an address inside the TIA that the TIA ignores, chooses the bank shown at
$1000-$17FF; the last bank is fixed at $1800-$1FFF. With an 8 KiB ROM there are four banks and the
number is taken modulo four (6502.ts). The core starts with bank 0.
3E
As 3F, plus RAM: a write to $003F selects a ROM bank, a write to $003E selects one of up to 32 RAM banks of 1 KiB
in the same place. The RAM write port is the second half of that 2 KiB window. The explorer disassembles the ROM banks only.
FE (Activision)
8 KiB, two 4 KiB banks, with no hotspot address: the program switches by pushing or pulling the return address on the stack, and the
cartridge watches the bus. After an access to $01FE the next data byte’s bit 5 chooses the bank: set is bank 0, clear is
bank 1 (the 6502.ts logic). That is why a disassembly of such a ROM is only meaningful bank by bank.
UA (UA Limited)
8 KiB, two 4 KiB banks: touching $0220 selects bank 0 and $0240 bank 1 (addresses of the RIOT RAM mirror).
0840 (Economy Banking)
8 KiB, two 4 KiB banks: an access to an address whose bits give $0800 under the mask $1840 selects bank 0, one that gives
$0840 selects bank 1.
CV (CommaVid)
A 2 KiB ROM at $1800-$1FFF and 1 KiB of RAM in $1000-$17FF (read port $1000-$13FF, write port
$1400-$17FF). No bank switching. Not checked against a core.
DPC (Pitfall II)
Two 4 KiB program banks switched like F8, then 2 KiB of display data for the DPC coprocessor, whose registers occupy
$1000-$107F. The explorer shows the two banks as code and the display data as data. The chip’s registers are not described.
Not checked against a core.
AR (Supercharger)
A Supercharger ROM is a cassette image: loads of 8448 bytes, 8192 bytes of data and a 256-byte header, which the console’s own BIOS ROM reads. The program cannot be disassembled from the file alone, so the explorer lists the loads and shows no code. Not checked against a core.
SuperChip
An extra 128 bytes of RAM on the cartridge for F8, F6, F4 and EF ROMs: the write port is $1000-$107F and the read port
$1080-$10FF of every bank (6502.ts). The first 256 bytes of each bank are then not code. It is a checkbox in the options bar.
Unknown scheme
For a size no scheme above uses, every 4 KiB of the file is shown as a bank, and nothing is said about how they are switched.
Not described
Known, not yet covered
- Reference: the ARM schemes CDF, DPC+, BF, DF, the 28 KiB FA2, the 8195-byte “PP” image: 6502.ts supports them, this page does not describe them.
- Reference: the exact RAM read and write ports of E7 and CV beyond the sentence above.
Unknown
- Reference: CV, DPC and the Supercharger were not checked against a core.
- Reference: what the real chips do at power-up: the core’s start banks are its own choice, and a real cartridge usually starts in a random bank.