VGM file header

A VGM file starts with a 256-byte header in version 1.71. Integers are unsigned and little-endian, and offsets are hexadecimal. Pointers are relative to the field’s own position, so a VGM data offset of 0C at position 34 means the data starts at 40. Reserved bytes must be 0. This reference follows the VGM specification up to version 1.71; chips added after that are not listed here.

Fields

Offset	Size	Name	Version	Description
00	4	Ident	1.00	`Vgm` , with a trailing space.
04	4	EoF offset	1.00	Relative: file length minus 4.
08	4	Version	1.00	BCD: `00000171` is 1.71.
0C	4	SN76489 clock	1.00	0 when absent, like every chip clock. See clock bits.
10	4	YM2413 clock	1.00
14	4	GD3 offset	1.00	Relative offset of the GD3 tag, or 0.
18	4	Total samples	1.00	Length at 44,100 samples per second.
1C	4	Loop offset	1.00	Relative offset of the loop point, or 0.
20	4	Loop samples	1.00
24	4	Rate	1.01	The recording rate.
28	2	SN76489 feedback	1.10	Below.
2A	1	SN76489 shift width	1.10	Below.
2B	1	SN76489 flags	1.51	Below.
2C	4	YM2612/YM3438 clock	1.10
30	4	YM2151/YM2164 clock	1.10
34	4	VGM data offset	1.50	Relative offset of the data. Files before 1.50 start at `40`.
38	4	Sega PCM clock	1.51
3C	4	Sega PCM interface	1.51
40	4	RF5C68 clock	1.51
44	4	YM2203 clock	1.51
48	4	YM2608 clock	1.51
4C	4	YM2610/B clock	1.51
50	4	YM3812 clock	1.51
54	4	YM3526 clock	1.51
58	4	Y8950 clock	1.51
5C	4	YMF262 clock	1.51
60	4	YMF278B clock	1.51
64	4	YMF271 clock	1.51
68	4	YMZ280B clock	1.51
6C	4	RF5C164 clock	1.51
70	4	PWM clock	1.51
74	4	AY8910 clock	1.51
78	1	AY8910 chip type	1.51	Below.
79	1	AY8910 flags	1.51	Below.
7A	1	YM2203/AY8910 flags	1.51	Flags for the AY8910 inside a YM2203.
7B	1	YM2608/AY8910 flags	1.51	Flags for the AY8910 inside a YM2608.
7C	1	Volume modifier	1.60	Volume = 2^(value ÷ `20`), value −63 to 192; −63 is treated as −64.
7D	1	Reserved	1.60
7E	1	Loop base	1.60	Signed. Loops played = modified loops − loop base.
7F	1	Loop modifier	1.51	Loops played = program loops × modifier ÷ `10`. 0 is treated as `10`.
80	4	GameBoy DMG clock	1.61
84	4	NES APU clock	1.61
88	4	MultiPCM clock	1.61
8C	4	uPD7759 clock	1.61
90	4	OKIM6258 clock	1.61
94	1	OKIM6258 flags	1.61	Below.
95	1	K054539 flags	1.61	Below.
96	1	C140 chip type	1.61	Below.
97	1	Reserved	1.61
98	4	OKIM6295 clock	1.61
9C	4	K051649/K052539 clock	1.61
A0	4	K054539 clock	1.61
A4	4	HuC6280 clock	1.61
A8	4	C140 clock	1.61
AC	4	K053260 clock	1.61
B0	4	Pokey clock	1.61
B4	4	QSound clock	1.61
B8	4	SCSP clock	1.71
BC	4	Extra header offset	1.70	Relative offset of the extra header, or 0.
C0	4	WonderSwan clock	1.71
C4	4	Virtual Boy VSU clock	1.71
C8	4	SAA1099 clock	1.71
CC	4	ES5503 clock	1.71
D0	4	ES5505/ES5506 clock	1.71
D4	1	ES5503 channels	1.71	1 to 8, usually 2.
D5	1	ES5505/6 channels	1.71	1 to 4 for ES5505, 1 to 8 for ES5506, usually 1.
D6	1	C352 clock divider	1.71	Divider = value × 4, 0 to 1,020; usually 288.
D7	1	Reserved	1.71
D8	4	Seta X1-010 clock	1.71
DC	4	Namco C352 clock	1.71
E0	4	Irem GA20 clock	1.71
E4	28	Reserved		To `FF`.

From version 1.50 the header can be shorter: anything at or after the data offset at 34 is not header and can be ignored.

Clock bits

Bit 30 (40000000) of a chip clock means two chips of that type are present. The specification allows it for the PSG, YM2413, YM2612, YM2151, Sega PCM, YM2203, YM2608, YM2610, YM3812, YM3526, Y8950, YMZ280B, YMF262, YMF278B, YMF271, AY8910, GameBoy DMG, NES APU, MultiPCM, uPD7759, OKIM6258, OKIM6295, K051649, K054539, HuC6280, C140, K053260, Pokey, SCSP, WonderSwan, VSU, SAA1099, ES5503, ES5506, X1-010, C352 and GA20. Bit 31 (80000000) has a meaning of its own for some chips:

Offset	Chip	Bit 31 set
0C	SN76489	T6W28 (with bit 30)
10	YM2413	VRC7 (1.51 and later)
2C	YM2612	YM3438 (1.51 and later)
30	YM2151	YM2164 (1.51 and later)
4C	YM2610	YM2610B
50	YM3812	Pan the first chip left and the second right, with two chips, as on the Sound Blaster Pro 1 and Pro Audio Spectrum
84	NES APU	Enable the FDS sound add-on
8C	uPD7759	Slave (clear: master)
98	OKIM6295	The status of pin 7
9C	K051649	K052539
D0	ES5505/ES5506	ES5506 (clear: ES5505)
DC	C352	Disable the rear channels (clear: enabled)

SN76489 fields

Field	Values
Feedback (`28`)	`0009` Sega Master System, Game Gear and Mega Drive; `0003` Sega Computer 3000H and BBC Micro; `0006` SN76494 and SN76496. Files before 1.10 assume `0009`.
Shift width (`2A`)	16 for Sega systems, 15 for Sega Computer 3000H and BBC Micro. Files before 1.10 assume 16.

Flags bit (`2B`)	Meaning
0	Frequency 0 is `400`.
1	Negate the output.
2	Stereo on when clear.
3	÷8 clock divider on when clear.
4	XNOR noise feedback (NCR8496).
5–7	Reserved, 0.

AY8910 fields

Chip type (`78`)	Chip
`00`	AY8910
`01`	AY8912
`02`	AY8913
`03`	AY8930
`10`	YM2149
`11`	YM3439
`12`	YMZ284
`13`	YMZ294

Flags bit (`79`; default `01`)	Meaning
0	Legacy output.
1	Single output.
2	Discrete output.
3	RAW output.
4	YM2149 pin 26: an additional ÷2 clock divider.
5–6	Reserved, 0.
7	ZX-Spectrum-like pan configuration (left, centre, right).

OKIM6258 flags

Bits (default `00`)	Meaning
0–1	Clock divider: 1,024, 768, 512 or 512.
2	3-bit or 4-bit ADPCM (default 4-bit; noted as not working).
3	10-bit or 12-bit output (default 10-bit).
4–7	Reserved, 0.

K054539 flags

Bits (default `01`)	Meaning
0	Reverse stereo.
1	Disable reverb.
2	Update at key-on.
3–7	Reserved, 0.

C140 chip type

Value	Chip
`00`	C140, Namco System 2
`01`	C140, Namco System 21
`02`	219 ASIC, Namco NA-1 and NA-2

Extra header (1.70)

Placed between the main header and the VGM data, found through the field at BC.

Offset	Size	Name	Description
00	4	Header size	Size of the extra header; 4 or more.
04	4	Chip clock offset	Relative offset of the chip clock list.
08	4	Chip volume offset	Relative offset of the chip volume list.

List	Layout
Chip clocks	One byte: the number of entries. Each entry is 5 bytes: a chip ID, then the 32-bit clock of the second chip of that type.
Chip volumes	One byte: the number of entries. Each entry is 4 bytes: chip ID, flags, a 16-bit volume.

In a volume entry, bit 7 of the chip ID marks the volume of a paired chip (such as the AY part of a YM2203), and bit 0 of the flags the second chip. If bit 15 of the volume is clear, the value is absolute; if set, the chip’s volume is multiplied by (value & 7FFF) ÷ 100.

Version history

Version	Added
1.00	The first version.
1.01	Rate.
1.10	PSG feedback and shift register width.
1.50	Data offset and data blocks.
1.51	Many chips and commands, SN76489 flags and the loop modifier.
1.60	PCM RAM writes, DAC stream control, volume modifier and loop base.
1.61	More chips and data blocks.
1.70	The extra header.
1.71	More chips, command `31` for AY8910 stereo masks and the XNOR noise flag.

.VGM File Format – Header