A C64 has one SID chip at $D400, three voices. Some tunes were written for
two or three chips (an extra chip on a cartridge, or a second C64 with a cable), and since
version 3 the header says where the extra chips are. The first chip is always at
$D400. A chip’s registers take 32 bytes ($20), of which the first 29
are used (SID registers).
Versions 3 and 4: one byte for each extra chip
The byte at +7A (version 3 and 4) is the second chip’s address and the byte at
+7B (version 4) is the third’s. A byte b means the address
$D000 + b × 16, so $42 is $D420 and $FE is
$DFE0. Only even values are valid, in two ranges:
| Byte | Addresses | |
|---|---|---|
$00 to $41 | $D000 to $D410 | invalid (the VIC-II and the first SID): no chip |
$42 to $7E | $D420 to $D7E0 | valid (the area that mirrors SID 1 on a plain C64) |
$80 to $DF | $D800 to $DDF0 | invalid (colour RAM and the CIA chips) |
$E0 to $FE | $DE00 to $DFE0 | valid (the I/O areas of cartridges) |
| odd values | invalid |
Any invalid value, including 0, means there is no such chip. The third chip cannot be at the same address as the second. Version 2 files must have 0 in both bytes; version 3 files 0 in the third.
The SID model of each chip comes from the flags: bits 4 and 5 for the first, bits 6 and 7 for the second, bits 8 and 9 for the third (version 4). Unknown (0) for the second or third chip means the same model as the first. The explorer shows an address byte it cannot use as “not valid: no second SID”.
Version 5: up to 15 chips from a configuration
Version 5 replaces the two bytes with multiSidConfig at +7A and
sidAddressConfigStart at +7B. A single-SID file has 0 in both. The low
four bits of multiSidConfig are the total number of chips including the first
(2 to 15); the high four bits pick how the addresses of chips 2, 3, 4 … are made:
each address is the previous plus a step, and for the alternating configurations the two steps
are used in turn.
| Config | Step | Standard start of SID 2 | Addresses at the standard start | Most chips |
|---|---|---|---|---|
| 0 | +$20 | $D420 | $D420, $D440, $D460, $D480 … | 15 |
| 1 | +$40 | $D440 | $D440, $D480, $D4C0, $D500 … | 15 |
| 2 | +$80 | $D480 | $D480, $D500, $D580, $D600 … | 12 |
| 3 | +$100 | $D500 | $D500, $D600, $D700, $DE00, $DF00 | 6 |
| 4 | +$20, +$60 | $D420 | $D420, $D480, $D4A0, $D500 … | 15 |
| 5 | +$20, +$E0 | $D420 | $D420, $D500, $D520, $D600 … | 12 |
| 6 | +$100, +$300 | $D500 | $D500, $DE00, $DF00 | 4 |
| 7 to 15 | Reserved: must not be used. | |||
Addresses may only be generated in $D400–$D7E0 and
$DE00–$DFE0. A step that goes past $D7E0 carries on in
$DE00, keeping any remainder ($D800 becomes $DE00), and
a step past $DFE0 ends the list. A header that asks for more chips than the
configuration can make must be rejected.
sidAddressConfigStart may move the start of SID 2: a value of $42 to
$7E or $E0 to $FE (even), read like the version 3 byte, gives
SID 2’s address, and 0 or anything else means the configuration’s standard start. After an
explicit start, an alternating configuration uses its first step from SID 2 to SID 3. For
example configuration 3 starting at $E0 makes SID 2 at $DE00 and SID 3 at
$DF00 and no more; configuration 0 starting at $60 makes $D600,
$D620, $D640 …
All chips have the model of flag bits 4 and 5 in version 5. If the FM OPL flag (bit 11) is set,
$DF00–$DFFF belongs to the FM chip and no SID may be there.
Stereo panning (version 5)
Flag bits 6 and 7 choose a layout and bits 8 and 9 a mode. The result is a position, left (L), centre (C) or right (R), for each chip. A player that cannot pan may ignore it. A single chip is always centred.
| Layout (bits 6–7) | Rule |
|---|---|
| 00 Standard | L, R, L, R … starting with L. |
| 01 L/C/R | L, C, R, L, C, R … starting with L. |
| 10 Center first | The first C chips are centred, where C = N − 2 × floor(N/3), then L, R alternately starting with L. |
| 11 Fully centred | Every chip is centred. |
| Mode (bits 8–9) | What it does to the layout |
|---|---|
| 00 Direct | The layout as it is. |
| 01 Reverse | Swap L and R. For Center first, the centred chips are moved to the end. Fully centred stays centred. |
| 10 Group | Standard: pairs of chips, L L R R L L … (two chips are L R). L/C/R: all the L, then all the C, then all the R, in one group of up to 9 chips, or a group of 6 and a group for the rest. Center first: the centred chips, then L and R in blocks. |
| 11 Spread | Contiguous blocks across the field: Standard splits the chips in two (the left half gets the extra chip), L/C/R and Center first give floor(N/3) chips to each of L and R and the rest to C. |
With four chips: Standard direct is L R L R, reverse is R L R L, group is L L R R and spread is L L R R. L/C/R direct is L C R L, group and spread are L C C R. Center first direct is C C L R and reverse is R L C C. The explorer’s own implementation of the four layouts and four modes is checked, for one to fifteen chips, against every table in the format document.
How the explorer plays several chips
Each chip is its own emulated SID at its own address; a write to the I/O area goes to the chip that owns the
address, and the C64’s own mirroring of $D400 through $D7FF still goes to SID 1
for the addresses no other chip claims. The mix is in stereo: a chip on the left or the right goes to that
side, a centred chip to both at −3 dB. Versions 3 and 4 have no panning field, so the explorer places the
chips alternately left and right, as the Standard layout does.